Redundancy circuit of semiconductor memory

Details Redundancy circuit of semiconductor memory Redundancy circuit of semiconductor memory

2001-05-22

2002-05-21

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230030

Reexamination Certificate

active

06392937

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory including a redundancy circuit for relieving a defective memory cell.
In general, a semiconductor memory has a redundancy circuit for improving the yield of a product. When a defective memory cell exists within a memory cell array (a normal cell array), the redundancy circuit has a function of replacing this defective memory cell with a redundancy memory cell within a spare memory cell array.
At present, it is most general that a redundancy circuit employs a system of replacing a defective memory cell with a redundancy memory cell in a relief unit (replacement unit). The relief unit is a set of memory cells that are replaced at the same time when a defective memory cell is replaced with a redundancy memory cell. Generally, the relief unit is set in either memory cells that are connected to one or a plurality of word lines (row unit), or in memory cells that are connected to one or a plurality of pairs of bit lines (column unit).
When memory cells connected to a plurality of word lines (a plurality of rows) are set as a relief unit, for example, these plurality of word lines are connected to one row decoder, and a defective memory cell is replaced with a redundancy memory cell in a row decoder unit. Further, when memory cells connected to a plurality of pairs of bit lines (a plurality of columns) are set as a relief unit, for example, the plurality of pairs of bit lines are connected to one pair of I/O (Input/Output) lines, and a defective memory cell is replaced with a redundancy memory cell in a unit of the pair of I/O lines.
Further, in the case of a semiconductor memory structured by a plurality of banks that can be accessed substantially simultaneously, one bank (a memory cell array having a constant memory capacity) is set as a relief block unit. The relief block unit is a range in which a replacement in relief unit is effective. In other words, in this case, a defective memory cell is replaced with a redundancy memory cell in each relief unit within one relief block unit. More specifically, a defective memory cell within one bank can be replaced with only a redundancy memory cell within this bank, and the defective memory cell cannot be replaced with a redundancy memory cell within other banks.
In order to replace a defective memory cell with a redundancy memory cell in each relief unit, it is necessary to register in advance an address (a fail address) for specifying a relief unit having a defective memory cell in an address registration memory (for example, a fuse set). Further, it is also necessary to make a decision as to whether or not an external address or an internal address coincides with this fail address at the time of operating the semiconductor memory.
Accordingly, each of the plurality of banks within the semiconductor memory (a memory chip) has address registration memories (fail address memories) by the number equal to that of the relief units. The fail address memories are structured by nonvolatile memories. At present, a fuse is mainly used for the nonvolatile memory. A fail address memory structured by this fuse is called a fuse set.
Relief units and fuse sets are disposed at a ratio of one to one within one bank. In other words, the number of fuse sets within one bank is equal to the number of relief units in this bank.
A fuse set includes a plurality of fuse elements for storing fail addresses. One fuse element can store one bit data depending on whether this fuse element is to be disconnected or not. Accordingly, an N-bit fail address can be stored in N fuse elements.
A structure of the fuse set is simple, and the system for storing fail addresses in a fuse set is most widely employed at present.
FIG. 1
shows a main portion of a semiconductor memory having fuse sets.
In the present example, the semiconductor memory has a plurality of banks that can be accessed substantially simultaneously. One bank forms a relief block unit and one row decoder forms a relief unit.
A memory cell array is structured by eight sub-arrays
10
. One sub-array
10
is disposed within one bank BANKi (i=0, 1, . . . 7). In this case, eight banks BANK0, BANK1, . . . BANK7 are adjacently disposed in a column direction, for example. Each BANKi (i=0, 1, . . . 7) includes a normal cell array
11
, a spare cell array
12
, a row decoder
13
, a fixed spare row decoder
14
, and a fixed fuse set
15
.
The normal cell array
11
has a memory capacity of 512 kilobits, for example. On the normal cell array
11
, there are disposed 512 word lines
16
and 1,024 pairs of bit lines. In the present example, the number of the row decoders
13
is set to 128, and four word lines
16
are connected to one row decoder.
The spare cell array
12
has a memory capacity of sixteen kilobits, for example. On the spare memory cell array
12
, there are disposed sixteen spare word lines
17
and 1,024 pairs of bit lines. The number of the fixed spare row decoders
14
is set to four. The four spare word lines
17
are connected to one fixed spare row decoder.
A column decoder
19
is disposed adjacent to the bank BANK7 positioned at the last end of the eight banks BANK0, BANK1, . . . BANK7. A column select line CSL
18
is common to the eight banks BANK0, BANK1, . . . BANK7, and is disposed above the eight banks BANK0, BANK1, . . . BANK7. The column select line
18
extends to the BANK0 side from the column decoder
19
.
In the present example, one bank is set as a relief block unit, one row decoder (four word lines) is set as a relief unit, and four fixed spare row decoders are disposed within one bank. Therefore, it is possible to replace maximum four row decoders with fixed spare row decoders within one bank.
In other words, when a defective memory cell is included within the normal cell array
11
, and also when four or less row decoders out of the 128 row decoders are connected to the defective memory cell, it is possible to replace these defective row decoders with the fixed spare row decoders. As a result, a fraction of defective semiconductor memories can be decreased, and the yield of the products (productivity) can be improved.
Within each bank BANKi (i=0, 1, . . . 7), four fixed fuse sets
15
are provided corresponding to four fixed spare row decoders
14
. Each fixed fuse set can store one fail address.
An input address (an external address or an internal address) is input to each fixed fuse set. When the input addresses disagree with the fail addresses in all the fixed fuse sets, for example, the row decoders
13
become active (DISABLE F=“1”), and all the fixed spare row decoders
14
become inactive.
Further, when the input address coincides with the fail address in at least one of the fixed fuse sets, the row decoder
13
becomes inactive (DISABLE F=“0”), and the fixed spare row decoder corresponding to the at least one of the fixed fuse sets becomes active.
FIG. 2
shows an example of a fixed fuse set within a bank.
In the present example, the four fixed spare row decoders in
FIG. 1
correspond to the four fixed fuse sets
15
. Accordingly, when the semiconductor memory is structured by eight banks as shown in the example of
FIG. 1
, the fixed spare row decoders and the fixed fuse sets are provided by thirty-two (=4×8) within the semiconductor memory (memory chip).
When there exist 128 (=2
7
) row decoders within one bank as shown in the example of
FIG. 1
, seven-bit address signals A
0
, A
1
, . . . A
6
are necessary in order to specify one of the 128 row decoders. Therefore, in order to store a fail address, at least seven fuse units (fuse elements)
20
are necessary.
In the present example, one fuse unit (fuse element)
20
′ is provided as an enable fuse unit for determining whether the fixed fuse set
15
is to be used or not. Accordingly, within one fixed fuse set
15
F, the fuse units
20
and
20
′ are provided by eight in total.
One fuse unit is structured by a p-channel MOS transistor Qp, an n-channel MOS transistor Qn,

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