Semiconductor memory

Details Semiconductor memory Semiconductor memory

1999-06-23

2002-09-10

Jackson, Jr., Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S300000, C257S301000, C257S310000, C438S238000, C438S239000, C438S386000, C438S399000

Reexamination Certificate

active

06448598

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory using an insulating metal oxide as a capacitor dielectric film.
A conventional semiconductor memory will now be described with reference to FIG.
6
.
As shown in
FIG. 6
, a source region
32
, a drain region
33
and a gate portion of a transfer gate having a function as a transistor of a memory cell are formed on a silicon substrate
31
, and the gate portion includes a gate electrode
34
serving as a word line and an insulating film
34
R covering the gate electrode
34
. The drain region
33
is connected with a bit line
35
.
Transistors each including the source region
32
, the drain region
33
, the gate electrode
34
and the like are disposed on the silicon substrate
31
in the form of an array so as to constitute a memory cell array, but the memory cell array is omitted in FIG.
6
.
On the transistor, a first insulating layer
36
is formed, and the top surface of the first insulating layer
36
is flattened. In the first insulating layer
36
, a contact hole
37
connected with the source region
32
is formed, and a conductive plug
38
is buried in the contact hole
37
.
On the plug
38
, a lower electrode
39
and a capacitive insulting film
40
of an insulating metal oxide processed by dry etching are formed, and on the side surfaces of the lower electrode
39
and the capacitor dielectric film
40
, side walls
41
are formed. On the capacitor dielectric film
40
, an upper electrode
42
is formed. The lower electrode
39
, the capacitor dielectric film
40
and the upper electrode
42
together form a capacitor.
A second insulating layer
43
is formed so as to cover the capacitor. In the second insulating layer
43
, a contact hole
44
reaching the upper electrode
42
is formed, and in the contact hole
44
, a conductive metal wire
45
is formed.
In this conventional semiconductor memory, in forming the capacitor dielectric film
40
through the dry etching, strain derived from ion collision is caused in the crystal structure of the processed area of the capacitor dielectric film
40
. As the capacitor has a finer structure, this strain more harmfully affects the electrical characteristic. As a result, the breakdown voltage of the capacitor is lowered.
SUMMARY OF THE INVENTION
An object of the invention is providing a semiconductor memory including a capacitor with a high breakdown voltage and fabricated without conducting dry etching on a capacitor dielectric film.
In order to achieve the object, the first semiconductor memory of this invention comprises plural lower electrodes formed on a semiconductor substrate; a capacitor dielectric film of an insulating metal oxide continuously formed over the plural lower electrodes; plural upper electrodes formed on the capacitor dielectric film in, positions respectively corresponding to the plural lower electrodes; and plural transistors formed on the semiconductor substrate, wherein the plural lower electrodes are respectively connected with source regions of the plural transistors.
The second semiconductor memory of this invention comprises plural lower electrodes formed on a semiconductor substrate; a capacitor dielectric film of an insulating metal oxide continuously formed over the plural lower electrodes; an upper electrode formed over the capacitor dielectric film; and plural transistors formed on the semiconductor substrate, wherein the plural lower electrodes are respectively connected with source regions of the plural transistors.
In the first or second semiconductor memory, the capacitor dielectric film is formed continuously over the plural lower electrodes, and hence, there is no need to conduct dry etching for patterning the capacitor dielectric film. Accordingly, strain can be prevented from being caused in the crystal structure over the entire capacitor dielectric film, resulting in improving the breakdown voltage of the capacitor.
In the first or second semiconductor memory, an outer edge of the capacitor dielectric film is preferably positioned in an outside portion away, by 1 &mgr;m or more, from an outer edge of an outermost lower electrode among the plural lower electrodes.
In the first or second semiconductor memory, each of the upper electrodes is preferably made from a platinum film or a laminating film including a platinum film and an iridium oxide film.
In the first or second semiconductor memory, the capacitor dielectric film is preferably made of a bismuth layer shaped perovskite ferroelectric, strontium barium titanate or tantalum pentaoxide.


REFERENCES:
patent: 5486713 (1996-01-01), Koyama
patent: 5559666 (1996-09-01), Figura et al.
patent: 5568352 (1996-10-01), Hwang
patent: 5864153 (1999-01-01), Nagel et al.
patent: 5923062 (1999-07-01), Ohno
patent: 5932906 (1999-08-01), Shimizu
patent: 6198122 (2001-03-01), Habu et al.

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