Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-01-21
2002-05-14
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S344000, C257S357000, C257S408000
Reexamination Certificate
active
06388289
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Japanese Patent Application No. 11-019531, filed Jan. 28, 1999, the entire subject matter of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device and, more particularly, to a semiconductor device manufactured by a SOI-CMOS process.
2. Description of the Related Art
Currently, based on requirements for low power consumption and high integration, a CMOS-IC (Complementary Metal Oxide Semiconductor-integrated Circuit) is in the mainstream of semiconductor devices. Specifically, SOI (Silicon-On-Insulator) technology is used to further reduce power consumption, and to obtain high performance with low power. In a CMOS structure using SOI technology (hereinafter SOI-CMOS), a device element such as a transistor is isolated from other elements at its side surface by a LOCOS (Local Oxidation of Silicon) layer, and is isolated from a silicon substrate there below by a silicon oxide layer. Therefore, it is possible to reduce junction leakage current in SOI-CMOS. Further, as it is possible to design a transistor's characteristics regardless of the impurity in the semiconductor substrate, high performance with low power can be expected.
However, a conventional electrostatic discharge protection circuit cannot be used in a semiconductor device having a SOI-CMOS structure because the surge resistance per unit area of the device element (e.g. transistor) in a SOI-CMOS structure is lower than in a general CMOS structure. The reason why the conventional electrostatic discharge protection circuit can not be used in SOI-CMOS is explained below.
Referring to
FIG. 14
, an electrostatic discharge protection circuit
5000
includes a PMOS protection transistor
52
and an NMOS protection transistor
53
, which are connected together in series. The PMOS protection transistor
52
and the NMOS protection transistor
53
are respectively connected in parallel to a PMOS output transistor
50
and a NMOS output transistor
51
that are connected together in series. Drain electrodes of the transistors
50
,
51
,
52
,
53
are commonly connected to an output terminal
100
. A source electrode of the PMOS output transistor
50
and a gate electrode and a source electrode of the PMOS protection transistor
52
are connected to power supply
200
. A source electrode of the NMOS output transistor
51
and a gate electrode and a source electrode of the NMOS protection transistor
53
, are connected to ground
300
for an external connection. As the output transistors
50
,
51
are respectively connected in parallel to the protection transistors
52
,
53
, the electrostatic surge applied through the output terminal
100
can be branched into the output transistors
50
,
51
and the protection transistors
52
,
53
. That is why the circuit
5000
provides the electrostatic surge resistance.
Next, referring to
FIGS. 15 and 16
, the structural difference between the CMOS and the SOI-CMOS is explained using the NMOS transistors
51
,
53
as an example. In the conventional CMOS structure shown in
FIG. 15
, the NMOS output transistor
51
includes N-type diffusion layers
51
s
,
51
d
serving respectively as a source and a drain, a P-type substrate
60
sandwiched between the diffusion layers
51
s
,
51
d
serving as a channel region, and the gate electrode
51
g
which is disposed on the channel region
61
and formed on a thin gate oxide layer
74
. The NMOS protection transistor
53
has the same structure as the NMOS output transistor
51
. These NMOS transistors
51
and
53
are electrically isolated from each other by the LOCOS layer
70
. However, as the channel regions
61
of the NMOS transistors
51
and
53
are parts of the P-type substrate
60
, they are physically connected to each other.
On the other hand, in the conventional SOI-CMOS structure shown in
FIG. 16
, the structure of the NMOS transistors
51
,
53
is the same as the NMOS transistors used in the CMOS structure. The difference between the CMOS structure and the SOI-CMOS structure is that the NMOS transistors
51
and
53
are formed on an oxide layer
80
. Therefore, the channel region
60
of the NMOS output transistor
51
is isolated from the channel region
61
of the NMOS protection transistor
53
both electrically and physically.
The main reason why the NMOS transistors
51
,
53
are destroyed by the electrostatic surge is that a PN junction of a source or a drain is physically damaged by joule heat attendant to the surge current. Therefore, if a circuit has such a structure that the joule heat can not be diffused, the circuit is easily destroyed. In the CMOS structure, as the channel regions
61
is connected through the P-type substrate
60
, the joule heat which occurs at the PN junction of the source/drain and channel region is easily diffused. On the other hand, in the SOI-CMOS structure, as the NMOS transistors
51
,
53
are isolated from each other by the LOCOS layer
70
between them and the oxide layer
80
below them, it is difficult for the joule heat generated at the PN junction of the source/drain and channel region to be diffused away. Therefore, in the SOI-CMOS structure, it is easy for the PN junction to reach the critical temperature thereby be destroyed.
SUMMARY OF THE INVENTION
An objective of the invention is to resolve the above-described problem and to provide a semiconductor device having a SOI-CMOS whose an electrostatic discharge protection circuit can be kept small and which has an improved resistance to electrostatic destruction.
This objective is achieved by a semiconductor device manufactured by a SOI-CMOS process, that includes an output terminal and a ground terminal and a first electrostatic discharge protection circuit formed on an insulator, the first protection circuit including a first lightly doped diffusion layer of a first conductivity type, two first highly doped diffusion layers of the first conductivity type, and a first gate electrode formed on a gate insulating layer which is formed on the first lightly doped layer. The first lightly doped diffusion layer is sandwiched by the first highly doped layers. One of the first highly doped layers is connected to the output terminal and the first gate electrode is connected to the ground terminal. The source of a first conductivity type output transistor is connected to the ground terminal. The first protection circuit and the first conductivity type output transistor are connected to each other in series, between the output terminal and the ground terminal.
The objective is further achieved by adding to the semiconductor device described above, a second protection circuit which has the same structure and connection as the first protection circuit and a first conductivity type protection transistor. In this case, the second protection circuit and the first conductivity type protection transistor are connected to each other in series, and are connected in parallel to the first protection circuit and the output transistor, between the output terminal and the ground terminal.
The objective is further achieved by adding to either of the semiconductor devices described above, a third protection circuit and a second conductivity type protection transistor. In this case, the third protection circuit has a lightly doped diffusion layer of a second conductivity type, two highly doped diffusion layers of the second conductivity type, and a gate electrode formed on a gate insulating layer which is formed on the lightly doped layer. The gate electrode of the third protection circuit and a gate electrode of the second conductivity type protection transistor are commonly connected to a power supply. The second conductivity type protection transistor and the third protection circuit are connected to each other in series, and are connected in parallel to the first and/or second protection circuits, between the output terminal and the ground terminal.
REFERENCES:
patent:
Chaudhuri Olik
Ha Nathan W.
Mimura Junichi
Oki Electric Industry Co. Ltd.
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