MRAM architecture and system

Details MRAM architecture and system MRAM architecture and system

2001-01-30

2002-07-09

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S189011, C365S230030, C365S230010, C365S189090, C365S189020, C365S230020

Reexamination Certificate

active

06418046

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to magnetoresistive random access memories and more particularly to the architecture of magnetoresistive random access memories systems.
BACKGROUND OF THE INVENTION
The architecture for Magnetoresistive Random Access Memory (MRAM) is generally composed of a plurality or array of memory cells and a plurality of digit and bit line intersections. The magnetoresistive memory cell generally used is a magnetic tunnel junction (MTJ), an isolation transistor, and the intersection of digit and bit lines. The isolation transistor is generally a N-channel field effect transistor (FET). An interconnect stack connects the isolation transistor to the MTJ device to the bit line. The digit line is used to create part of the magnetic field for programming the MRAM cell.
MTJ memory cells generally include a non-magnetic conductor forming a lower electrical contact, a pinned magnetic layer, a tunnel barrier layer positioned on the pinned layer, and a free magnetic layer positioned on the tunnel barrier layer with an upper contact on the free magnetic layer.
The pinned layer of magnetic material has a magnetic vector that is always pointed in the same direction. The magnetic vector of the free layer is free, but constrained by the physical size of the layer, to point in either of two directions. An MTJ cell is used by connecting it in a circuit such that electricity flows vertically through the cell from one of the layers to the other. The MTJ cell can be electrically represented as a resistor and the size of the resistance depends upon the orientation of the magnetic vectors. As is understood by those skilled in the art, the MTJ cell has a relatively high resistance when the magnetic vectors are misaligned (point in opposite directions) and a relatively low resistance when the magnetic vectors are aligned. Additional information as to the fabrication and operation of MTJ memory cells can be found in U.S. Pat. No. 5,702,831, entitled “Multi-Layer Magnetic Tunneling Junction Memory Cells”, issued 31 Mar. 31, 1998, and incorporated herein by reference.
A bit line is generally associated with each column of an array of MTJ cells and a digit line is associated with each row of the array. The bit lines and digit lines are used to address individual cells in the array for both reading and programming or storing information in the array. Programming of a selected cell is accomplished by passing predetermined currents through the digit and bit lines intersecting at the selected cell. The currents create a magnetic field that sets the magnetic vector in the free layer to a desired position. Several problems are prevalent in the standard memory architecture, including high programming currents, insufficient space on the substrate to conveniently carry all of the related components, and memory system timing to effectively utilize a memory cycle during read and program operations.
Thus, it is desirable to provide an improved architecture for MRAM memories that overcome some or all of these problems and an improved system of operation.


REFERENCES:
patent: 5946227 (1999-08-01), Naji
patent: 6055178 (2000-04-01), Naji
patent: 6134060 (2000-10-01), Ryat

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