Thin film transistor and method of fabricating the same

Details Thin film transistor and method of fabricating the same Thin film transistor and method of fabricating the same

2001-03-19

2002-09-24

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S978000, C438S713000

Reexamination Certificate

active

06455357

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a thin film transistor and a method of fabricating the thin film transistor.
2. Background of the Related Art
Thin film transistors serve as switching devices switching image data signals in each pixel region. Thin film transistors can be used instead of CMOS load transistors or load resistors of a static random access memory (SRAM) of more than 1M bit. A liquid crystal display (LCD) includes an upper glass, a lower glass, and a liquid crystal interposed between the upper and lower glasses. The upper glass has a black matrix layer, a common electrode, and R, G and B color filter layers. The lower glass has data lines and gate lines crossing each other and pixel regions arranged in matrix. A pixel electrode is formed in each pixel region, and an amorphous thin film transistor acting like an analog switch is formed to control charge stored in its capacitor.
FIG. 1
is a lay-out of a related art liquid crystal display. As shown in
FIG. 1
, the lower glass includes a plurality of scanning lines
11
formed extending in one direction, a gate electrode
11
a
extending from each scanning line
11
and data lines
12
crossing the scanning lines
11
. A thin film transistor includes a source electrode
12
a
and a drain electrode
12
b
extending from the data lines
12
.
Black matrix layers (not shown) are arranged on the upper glass like a gauze to shut out the light in a region except the pixel electrodes (not shown) formed on the lower glass. R, G and B color filter layers (not shown) are formed between the black matrix layers. Further, a common electrode (not shown) is formed over the color filter layers and black matrix layers.
As shown in
FIG. 2
, a related art thin film transistor includes a gate electrode
11
a
formed on an insulating substrate
21
, a gate insulating layer
22
disposed on gate electrode
11
a
and an amorphous silicon layer
23
disposed on gate insulating layer
22
to enclose the gate electrode
11
a.
An n+ silicon layer is formed as an ohmic layer
24
to expose a part of the amorphous silicon layer
23
on the gate electrode
11
a,
and the source electrode
12
a
and the drain electrode
12
b
are formed on the ohmic layer
24
. The material of each of the source and drain electrodes
12
a
and
12
b
is molybdenum.
The process of manufacturing a related art thin film transistor will now be described. As shown in
FIG. 3A
, the gate electrode
11
a
is formed on a predetermined area of the insulating substrate
21
. An insulating layer such as siliconitride SiN is formed on the substrate
21
including the gate electrode
11
a
to form the gate insulating layer
22
. The insulating material used as the gate insulating layer
22
serves as a capacitor dielectric in a storage capacitor area. As shown in
FIG. 3B
, an amorphous silicon layer
32
and an n+ silicon layer
33
are formed on the gate insulating layer
22
.
As shown in
FIG. 3C
, the n+ silicon layer
33
and the amorphous silicon layer
32
are selectively removed to enclose the gate electrode
11
a.
Molybdenum (Mo) is applied all over substrate
21
including the n+ silicon layer
33
as source and drain electrodes. The molybdenum material forming the source and drain electrodes and the n+ silicon layer
33
are serially etched to expose the amorphous silicon layer
32
corresponding to a channel region and form the source and drain electrodes
12
a
and
12
b.
Molybdenum (not shown), the material forming the source and drain electrodes, is patterned on the gate insulating layer
22
in the storage capacitor area of the pixel region to contact a pixel electrode in the post manufacturing process.
As shown in
FIG. 3D
, a passivation layer
34
is formed all over the substrate
21
including the source and drain electrodes
12
a
and
12
b.
Thus, the manufacture of the thin film transistor is complete.
In the manufacture of the thin film transistor, when fluorine (F) gas is used as an etching gas in an etching process to form source and drain electrodes, an etching selection ratio of n+ silicon layer
33
and amorphous silicon layer
32
cannot be secured. Thus, Chlorine (Cl) gas is used instead of the fluorine gas to solve the above problem. When using Cl gas, there is no etching selection ratio with gate insulating layer
22
of the storage capacitor area, which causes excessive etching of gate insulating layer
22
, and, what is worse, gate insulating layer
22
may be opened.
A second related art thin film transistor was proposed to solve the above problem, and a method of fabricating the second related art thin film transistor will now be described.
FIGS. 4A
to
4
J depict the steps in the manufacture of the second related art thin film transistor.
As shown in
FIG. 4A
, a gate material
44
formed of chromium
42
and molybdenum
43
is formed on a predetermined area of substrate
41
. The gate material
44
can be constituted by either two layers (e.g., chromium
42
and molybdenum
43
) or one layer.
Referring to
FIG. 4B
, the gate material
44
is patterned to form a gate electrode
44
a
by a general patterning process. Sides of the gate electrode
44
a
have a slant when formed by a reactive ion etching (RIE) when patterning the two-layered gate electrode
44
a
formed by molybdenum
43
and chromium
42
.
As shown in
FIG. 4C
, after patterning the gate electrode
44
a,
a gate insulating layer
45
is deposited all over the gate electrode
44
a
and the substrate
41
. The gate electrode
44
a
is inclined at its edge to improve the coverage in the corresponding area. A gate electrode having a slant at its edge and a technique of improving the coverage are disclosed in U.S. Pat. No. 5,132,745.
As shown in
FIG. 4D
, an amorphous silicon layer
46
is serially deposited on the gate insulating layer
45
in a vacuum chamber. An n+ amorphous silicon layer
47
is serially deposited on the amorphous silicon layer
46
. Subsequently, as shown in
FIG. 4E
, the n+ amorphous silicon layer
47
and the amorphous silicon layer
46
are selectively removed except in an area where a thin film transistor is formed on, the substrate
41
.
As shown in
FIG. 4F
, a first conductive layer
48
is deposited to a thickness of 0.01 to 0.1 &mgr;m on the gate insulating layer
45
including the patterned n+ amorphous silicon layer
47
and the amorphous silicon layer
46
. The first conductive layer
48
is made of chromium (Cr) in ohmic contact with the n+ amorphous silicon layer
47
. The first conductive layer
48
can be made of a material such as nichromium (nickel and chromium) and tantalum.
A second conductive layer
49
is deposited to a thickness of 0.1 to 1 &mgr;m on the first conductive layer
48
. Thus, the second conductive layer
49
is relatively larger than the first conductive layer
48
. The second conductive layer
49
is made of molybdenum, and may be made of aluminum or tungsten. The use of molybdenum as second conductive layer
49
assures better conductivity than that of source and drain electrodes made of chromium (Cr), which constitutes the first conductive layer
48
. Molybdenum assures a good ohmic contact for source and drain electrodes and the n+ amorphous silicon layer
47
.
As shown in
FIG. 4G
, a photoresist
50
is applied on the second conductive material
49
. The photoresist
50
corresponding to the channel region of the thin film transistor is removed, and the photoresist
50
is patterned to have edges slanted by 45°.
As shown in
FIG. 4H
, the second conductive material
49
is etched using the photoresist
50
as a mask with a requirement that the first conductive layer
48
is not effected. Based on the requirement of the etching process, SF
6
gas of 37.5 sccm, Cl
2
gas of 6.5 sccm, and O
2
gas of 16 sccm are used and a pressure of 6.5 mTorr is maintained. The etching process is carried out under Rf plasma. Since the photoresist
50
is patterned with incline

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