Electrical computers and digital data processing systems: input/ – Input/output data processing – Data transfer specifying
Reexamination Certificate
1999-03-24
2002-01-08
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Data transfer specifying
C710S033000, C713S500000
Reexamination Certificate
active
06338103
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of computer systems having dynamic memory data storage and, more particularly, to a method and circuit architecture implementing pointers for enabling high-speed burst data transfer for computer and computing system applications.
2. Discussion of the Prior Art
With rapid improvements in computer processor performance, it is not only highly desirable to have main memories with high-density, but also with higher data rates. For example, with ever-increasing system clock rates of the state-of-the-art microprocessors, high band-width DRAM's are required in order to avoid wait states without adding to the complexity of memory hierarchy, e.g., such as when implementing SRAM cache. Prefetch architectures can effectively boost the burst frequency of the DRAM data rates. For example, a “2b” prefetch architecture has been introduced for synchronous DRAM (SDRAM) to boost the data-rate to 200%. It readily follows that a “4b” prefetch architecture may be used for the double data rate (DDR) SDRAM to boost the data-rate to 400%. An “8b” prefetch architecture is already used for the Rambus DRAM (RDRAM), realizing data rates of up to 800%.
Regardless of any prefetch architecture, a frequency conversion is required, for example, by multiplexing a plurality of data signals on a bus with slow speed for storage thereof at corresponding registers during a prefetch operation, and then reading the latched data signal sequentially from the registers to a shared bus at a high speed. A typical example of this frequency conversion is the first in first out (FIFO) circuitary comprising a plurality of registers, input pointers, and output pointers. A key design factor in FIFO circuitry is how to fetch the input data to the registers with input pointers and output the data from the registers with output pointers. Thus, there is a strong and potential requirement to design pointers for use in prefetching architecture, in particular FIFO circuitry.
FIG. 1
illustrates a typical pointer design, where the data on four registers
101
-
104
are transferred to one data output bus
110
in burst mode, e.g., four bit burst mode. Such burst data transfer assumes pre-fetch has taken place, i.e., the latches or registers
101
-
104
comprise the data, for e.g., input simultaneously at a first cycle time, e.g., 10 nsec. The burst transfer is realized by sequentially activating one of the four pointer signals
112
a
, . . . ,
112
d
. The problems of this prior art design are: 1) overlapping of two pointer signals causes a data contention on data output bus
110
; 2) insufficient pointer signal pulse width cannot drive the data output bus
110
, which may cause a functionality problem; and 3) it is difficult to globally transfer a small pulse width pointer signal, since the signal pulse may be severely degraded, modified, or even disappear due to the circuit wiring which acts as an RC low pass filter.
Overcoming these problems are more difficult as the burst data frequency is increased to speeds currently achievable, e.g., 2.5 nsec for 400 Mb/sec with 200 MHZ DDR operation.
It would thus be highly desirable to provide an improved circuit architecture implementing pointer signals that enable high-speed burst data transfer of digital signals from a plurality of drivers onto a data bus sequentially, in a simple and efficient manner.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a circuit architecture and circuit control methodology implementing high-speed burst mode data transfer, in a manner so as to avoid the aforementioned problems.
It is a further object of the present invention to provide a digital circuit architecture that implements overlapped “global-pointer” signals for generating non-overlapped “local-pointer” signals that enable the high-speed, sequential burst data transfer from a plurality of sources to a single data line in a simple and efficient manner.
It is a further object of the present invention to provide a control methodology for enabling generation of overlapped global and non-overlapped local pointer control signals for enabling high-speed, sequential burst data transfer from a plurality of sources to a single data bus in a simple and efficient manner. According to the principles of the invention, there is provided a circuit architecture and methodology for providing increased burst data transfer in high-speed digital circuit applications that implements a sequence of overlapped global-pointer signals for generating a corresponding sequence of non-overlapped local-pointer signals. One of the global pointer signals is activated per cycle and the pulse width of each global pointer signal is greater than the cycle time. A global pointer signal <i> of a sequence (where i is one of the integers <1:n>) generates a corresponding local pointer signal <i> that is reset by detecting a time at which the next successive global pointer signal <i+1> starts to be activated. This allows for generation of reliable non-overlapped local pointer signals, while using overlapped global pointer signals.
Advantageously, the invention is suited for multitasking computing system architectures implementing dynamic RAM and is capable of achieving data transfer rates of, e.g., 800 Mbits/sec/pin (corresponding to 400 MHZ system cycle) or greater, utilizing double-data synchronous or Rambus DRAM architectures with 8b prefetch or beyond.
REFERENCES:
patent: 4412335 (1983-10-01), Froment et al.
patent: 4670672 (1987-06-01), Ando et al.
patent: 4760291 (1988-07-01), Nakajima et al.
patent: 5003194 (1991-03-01), Engelhard
patent: 5173618 (1992-12-01), Eisenstadt
patent: 5218237 (1993-06-01), Mao
patent: 5389831 (1995-02-01), Eisenstadt
patent: 5517136 (1996-05-01), Harris et al.
patent: 5517638 (1996-05-01), Szczepanek
patent: 5748806 (1998-05-01), Gates
patent: 5828659 (1998-10-01), Teder et al.
patent: 6173190 (2001-01-01), Usui
patent: 6182183 (2001-01-01), Winghard et al.
Du Thuan
Lee Thomas
Schnurmann H. Daniel
Scully Scott Murphy & Presser
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