Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-10-17

2002-01-01

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Serial read/write

C365S230040

Reexamination Certificate

active

06335889

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device that performs data input to and data output from memory cells in bursts, and particularly to a semiconductor memory device that is provided with an operation mode in which data that are read from memory cells are outputted to the outside without being latched.
2. Description of the Related Art
In recent years, the operating speed of CPUs (Central Processing Units) has been increasing with each year along with the miniaturization of LSI (Large-Scale Integrated circuits). However, in spite of the increase in storage capacity of semiconductor memory devices such as DRAM (Dynamic Random Access Memory), the fact remains that greater memory capacity is accompanied by a corresponding increase in the wiring length, and the speed of these memory devices lags behind CPU speeds due to the delay resulting from the charging and discharging of word lines and bit lines.
This state has led to the implementation of various designs to realize an apparent increase in speed of the semiconductor memory device. One method that has been considered is using serial exchange of data with the outside of the semiconductor memory device while using parallel transfer of data between memory cells and other circuits inside the semiconductor memory device. Alternatively, it is possible to apply a DDR (Double Data Rate) technique by which input and output of data are performed at both the rise and fall of the basic clocks in the system that uses the semiconductor memory device, whereby input and output data are divided between two phases, the input and output operations of each phase are performed by parallel processing in the semiconductor memory device, and an internal processing period that corresponds to double the data input/output period is secured for the input/output data of each phase.
This type of semiconductor memory device may also be provided with several modes when reading serial data to the outside of the semiconductor memory device. As one of these modes, there is a mode in which, after once latching all bits of parallel data that have been simultaneously read from memory cells, the latched parallel data are then serially outputted to the outside (hereinbelow referred to as “latch mode”). In addition to this latch mode, there is a mode in which, to enable a shorter access time than that of latch mode, only the bit of the read parallel data that are to be outputted to outside the semiconductor memory device first are outputted “through” without latching (hereinbelow referred to as “through mode”).
FIG. 1
gives a schematic representation of the internal architecture adopted in a semiconductor memory device of the prior art. An explanation is next given of the operation when reading in bursts is performed from the memory cell arrays shown in this figure. A read address that is supplied from outside the semiconductor memory device is assumed to correspond to, for example, memory cells inside memory cell array
101
U. In this case, the data of, for example, 8 bits (bit
0
-bit
7
) corresponding to the designated read address are read in parallel from memory cell array
101
U and simultaneously supplied to data amplifier
107
U. Data amplifier
107
U supplies the four bits of even data to parallel-serial conversion circuit
108
U
e
and the four bits of odd data to parallel-serial conversion circuit
108
U
o.
Parallel-serial conversion circuit
108
U
e
converts the even data to four bits of serial data by sequentially outputting the received even data to selector
109
e
in synchronization with the fall of basic clock CLK. Parallel-serial conversion circuit
108
U
o
similarly converts the odd data to four bits of serial data by sequentially outputting the received odd data to selector
109
o
in synchronization with the rise of basic clocks CLK. Since data are read from memory cells
101
U as described in the foregoing explanation, selectors
109
e
and
109
o
select serial data that are supplied from parallel-serial conversion circuits
108
U
e
and
108
U
o
in accordance with selection signals U/L.
Multiplexer
110
selects the output of selectors
109
e
and
109
o
at the rise of and fall, respectively, of basic clocks CLK, and alternately outputs even data and odd data. The eight bits of serial data from bit
0
to bit
7
are thus outputted to the outside in a burst through an output buffer (not shown in the figure) and input/output pad
100
. In addition, read operations from memory cell array
101
L are also carried out according to the above-described operation, data in this case being sent through data amplifier
107
L and parallel-serial conversion circuits
108
L
e
and
108
L
o
and from selectors
109
e
and
109
o
to multiplexer
110
. Since the operation of writing to the memory cell arrays is not directly related to the problem to be solved, explanation is here omitted.
Thus, even if operations take place in accordance with a high-speed clock outside the semiconductor memory device, the read or write process can be carried out inside the semiconductor memory device at a period of eight times this clock because eight bits of data can be outputted to the outside or received from the outside in one instance of reading or writing, as described hereinabove. To describe in more specific terms, the architecture of the read system may be composed of memory cell arrays
101
U and
101
L and data amplifiers
107
U and
107
L for low speed; and by: parallel-serial conversion circuits
108
U
e
,
108
U
o
,
108
L
e
, and
108
L
o
; selectors
109
e
and
109
o
; multiplexer
110
; and input/output pad
100
for high speed. In this case, the length of wiring of the latter path is shorter than that of the former, and there are fewer constituent elements on the latter path than on the former path. As a result, the use of larger transistors has little effect on the size of a chip, making this architecture readily applicable to high-speed operation.
In a typical general-purpose clock-synchronized DRAM, however, there is variation in the locations in the memory cell array or each of the bits of data that are to be read in parallel from the memory cell array. In other words, the locations of all of the bits are distributed over the entire memory cell array with no relation between the bits of parallel data that are read first and the bits that are read last. In the prior art, therefore, processing is carried out by slowing the CPU to match the processing speed of the DRAM. For example, if the CAS (Column Address Strobe) latency is set to “3,” the CPU assigns the CAS signal to the DRAM and then waits “3 cycles” before receiving the read data from DRAM. Essentially, read time in the prior art is determined by the bit that takes the most time to read, thereby determining not only the specifications of the DRAM but the design of the system that uses the DRAM. Accordingly, the same level of high-speed access is demanded for all bits from bit
0
to bit
7
in a case in which eight bits of data are read in parallel from a memory cell array.
On the other hand, the type of semiconductor memory device that is taken as the object of the present invention has a fixed burst output as described hereinabove, and the data that are read from a memory cell array are sequentially outputted in a burst of, for example, an eight-bit portion from bit
0
to bit
7
. This order of output depends on the various operation modes such as the above-described latch mode or through mode and does not change, and it is determined in advance as a specification that the bit that is to be outputted first is always bit
0
.
Accordingly, in a semiconductor memory device having a fixed burst output, the demand for the reading of bit
0
is the most stringent regarding time, and the performance of the semiconductor memory device is governed by how fast this bit
0
is read. In particular, when the semiconductor memory device is operated in through mode, the data of bit
0
that is read from the memory cell array must

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