MIS transistor and method of fabricating the same

Details MIS transistor and method of fabricating the same MIS transistor and method of fabricating the same

1997-06-13

2002-03-19

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S900000, C257S382000, C257S408000

Reexamination Certificate

active

06359321

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a MIS transistor widely employed for an electronic circuit such as a semiconductor integrated circuit and a method of fabricating the same, and more particularly, it relates to a method of fabricating a MIS transistor through a salicide process employing a refractory metal silicide film for attaining a high speed and high reliability.
2. Description of the Background Art
An exemplary salicide (self-aligned silicide) process for forming a general refractory silicide film is described with reference to
FIGS. 47
to
50
.
First, a well
1
a
, isolation oxide films
2
, and an impurity layer
3
for controlling a threshold voltage are formed on a silicon substrate
1
. Thereafter a silicon oxide film
4
of 6.5 nm in thickness, for example, is formed on the silicon substrate
1
, and a polycrystalline silicon layer for defining a gate electrode is deposited on the oxide film
4
in a thickness of 200 nm. An impurity is added to this polycrystalline silicon layer, which in turn is patterned by a photolithographic step and thereafter anisotropically etched for forming a gate electrode
5
.
Then, LDD (lightly doped drain) layers
6
which are also referred to as extension layers are formed, and thereafter an oxide film is deposited by CVD (chemical vapor deposition). This oxide film is etched back by reactive ion etching (hereinafter referred to as RIE), for forming side walls
7
consisting of silicon oxide on right and left sides of the gate electrode
5
.
Then, high-concentration source/drain layers
8
are formed by high-concentration ion implantation, and thereafter heat treatment is performed for activation.
FIG. 47
is a sectional view showing a state after completion of the activation.
Then, the salicide process is carried out.
In the salicide process, a surface of the silicon substrate
1
is first cleaned by proper pretreatment, and thereafter a metal film
9
is deposited on the structure shown in
FIG. 47
(see FIG.
48
).
Then, this structure is heated under a proper atmosphere for forming silicide films
10
by the silicon substrate
1
and the polycrystalline silicon forming the gate electrode
5
(see FIG.
49
). The composition of these silicide films
10
is expressed as MSix, assuming that M represents a metal element forming the metal film
9
, for example, where x represents the ratio of silicon atoms to the metal atoms. In this case, a short-time heat treatment (rapid thermal annealing) is generally performed through a lamp annealing furnace. The heat treatment which is performed through the lamp annealing furnace immediately after deposition of the metal film
9
is hereafter referred to as first RTA.
At this time, no silicide reaction takes place on upper portions of the isolation oxide films
2
and the side walls
7
due to absence of silicon, and the unreacted metal film
9
remains at least on these upper portions (see FIG.
49
). Then, the metal film
9
still containing the unreacted metal M etc. is selectively removed while leaving the silicide films
10
formed by the reacted silicide MSix (see FIG.
50
). Basically, the salicide process is ended in the aforementioned step.
However, when the silicide films formed through the aforementioned process are made of titanium silicide TiSix, for example, further heat treatment is performed at a high temperature or over a long time for forming titanium silicide films of TiSi
2
having a different composition or structure, since the electric properties of titanium silicide TiSix are insufficient. Also in case of changing the composition or structure of titanium silicide, a short-time heat treatment is generally performed through a lamp annealing furnace. The short-time heat treatment employed for changing the composition or structure of such silicide films is hereinafter referred to as second RTA. Due to the salicide process employing the aforementioned steps, an electrode can advantageously be formed selectively only on a region exposing a silicon surface on the silicon substrate
1
.
In recent years, on the other hand, integrated circuits including MIS transistors are implemented with higher density of integration such that the gate length of a planar MOS transistor which is a kind of MIS transistor is refined and side wall widths are also refined in response thereto, for example. However, the conventional MIS transistor fabricated through the salicide process has the aforementioned structure and the silicide film formed on the gate electrode further grows onto the side walls. Due to the small gate length, therefore, the silicide film growing from the gate electrode is disadvantageously connected with those on the source/drain layers if things come to the worst, to result in short-circuiting across the gate electrode and the source/drain layers and deterioration of the yield.
FIG. 51
is a sectional view showing a region AR
1
, enclosed with dotted lines in
FIG. 50
, in an enlarged manner for illustrating extreme growth of the silicide film. If the diffusion species employed for forming the silicide films is prepared from silicon, short-circuiting is readily caused by creeping of silicide in case of titanium silicide TiSi
2
, for example.
Due to the aforementioned structure of the conventional MIS transistor fabricated through the salicide process, further, phase transition from a C49 phase to a C54 phase hardly takes place in the crystal structure even by second RTA in case of titanium silicide TiSi
2
when the gate length or a silicide wiring width is refined to below 0.5 &mgr;m, resulting in such a problem that the sheet resistance of the titanium silicide films is abruptly increased.
FIG. 52
shows exemplary gate dependency of gate resistance in titanium silicide TiSi
2
.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a method of fabricating a MIS transistor includes a gate electrode forming step of forming a gate electrode containing polycrystalline silicon which is opposed to a silicon substrate through a gate insulating film, a side wall forming step of forming side walls on both sides of the gate electrode, and a salicide step of forming desired silicide films on upper portions of the gate electrode and a source/drain layer, and the side wall forming step has steps of depositing a first insulating film on a region including at least one of the both sides of the gate electrode and a surface of the silicon substrate which is allowed to be exposed by the gate electrode and in contact with the at least one of said both sides, depositing a second insulating film which is opposed to the at least one of said both sides and the surface through the first insulating film, and etching back the first and second insulating films thereby forming the at least one of the both sides walls of a two-layer structure, and the method further includes an etching step of etching the first insulating film in a larger amount than the second insulating film before the salicide step.
According to a second aspect of the present invention, compositions of the first and second insulating films are different from each other, and the etching step is adapted to isotropically etch the first insulating film.
According to a third aspect of the present invention, compositions of the first and second insulating films are different from each other, and the etching step is adapted to etch the first insulating film through anisotropic etching at a higher etching rate in a vertical direction which is perpendicular to the silicon substrate as compared with an etching rate in a horizontal width direction.
According to a fourth aspect of the present invention, the method further includes a step of roughening an upper surface of the gate electrode before the salicide step.
The present invention is also directed to a MIS transistor. According to a fifth aspect of the present invention, a MIS transistor includes a gate electrode which is formed to be opposed to a silicon substrate through a gate insulating film and has a silici

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