Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-07
2002-03-26
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S602000, C257S610000, C257S647000
Reexamination Certificate
active
06362510
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to a method for substantially preventing the migration of dopants into the channel region and improving active device isolation within an integrated circuit, and further to a similarly enhanced semiconductor topography. 2. Description of the Related Art
Fabrication of metal-oxide-semiconductor (“MOS”) transistors is well known. Active areas of a lightly doped silicon substrate in which the transistors and other active devices will reside are first isolated from other active areas with isolation structures. The regions in which the isolation structures are formed are termed field regions. A gate oxide (i.e., silicon dioxide) layer is then formed upon the substrate by thermal oxidation. Next, a gate conductor is formed upon the gate oxide layer by depositing polycrystalline silicon (“polysilicon”) and then patterning the polysilicon. A high dosage of n-type or p-type dopants is then concurrently implanted into the gate conductor and into source/drain regions arranged on opposite sides of the gate conductor within the silicon substrate. If the impurity dopant is n-type, then the resulting transistor is referred to as an NMOS device. Conversely, if the impurity dopant is p-type, then the resulting transistor is referred to as a PMOS device. An integrated circuit that employs both NMOS and PMOS devices is generally known as a complementary MOS or CMOS circuit.
The introduction of dopants into the gate conductor reduces its resistivity. In some instances, enough dopants are implanted to reduce the sheet resistivity of the gate conductor to less than approximately 500 ohms/sq. When using ion implantation processes, the depth to which the dopant ions are implanted can be controlled by adjusting the energy provided to the ions by the ion implantation equipment. The minimum depth of implantation, however, is usually limited to between 200 and 400 angstroms because the energy of each ion is typically too large to permit a lesser depth of implantation. Consequently, the implant depth of the dopants in the gate in the gate conductor is often deeper than would be ideal.
Subsequent processing steps usually require heating of the semiconductor topography. For example, a post-implant anneal is often performed to position and activate the dopants implanted into the source/drain regions and the gate conductor. During such heat processing, dopants with a high diffusivity typically migrate to greater depths within the polysilicon gate than dopants with a low diffusivity. For instance, boron, which is commonly used to dope the polysilicon gate and the source/drain regions of a PMOS device, is a fast diffuser. On the other hand, arsenic, which is typically used to dope the polysilicon gate and the source/drain regions of an NMOS device, is a slow diffuser. Unfortunately, heat treatment can cause dopants that readily migrate, like boron, to diffuse from the gate conductor through the gate oxide and into the channel region of the transistor. Boron penetration into the channel can lead to undesirable effects, such as an increase in electron trapping, a decrease in low-field hole mobility, degradation of the transistor drive current, and increased subthreshold current.
In addition, the increased desire to build faster and more complex integrated circuits has necessitated further reduction of the transistor threshold voltage, V
T
. Several factors contribute to V
T
, one of which is the effective channel length (“L
eff
”) of the transistor. The initial distance between the source-side junction and the drain-side junction of a transistor is often referred to as the physical channel length, L. However, after implantation and subsequent diffusion of the junctions, the electrical distance between junctions becomes less than the physical channel length and is commonly referred to as the effective channel length, L
eff
. In VLSI and ULSI designs, as the physical channel length decreases, so too must L
eff
. Decreasing L
eff
reduces the distance between the depletion regions associated with the source and drain of a transistor. As a result, less gate charge is required to invert the channel of a transistor having a short L
eff
. Reducing L
eff
can lead to a reduction in the threshold voltage of a transistor. The switching speed of the logic gates of an integrated circuit employing transistors with reduced threshold voltages is faster, which allows such an integrated circuit to more quickly transition between logic states (i.e., operate at high frequencies). Minimizing L
eff
also improves the speed of integrated circuits that include a large number of individual transistors because the larger drain current associated with a shorter effective channel length can drive the adjoining transistors into saturation more quickly. Furthermore, a smaller L
eff
reduces parasitic capacitances. Minimizing L
eff
is, therefore, desirable from a device operation standpoint.
Furthermore, minimizing L
eff
is desirable from a manufacturing perspective because the area of silicon required to manufacture a transistor having a smaller gate length is generally reduced. By minimizing the area required for a given transistor, the number of transistors available for a given area of silicon increases, which affords a corresponding increase in the circuit complexity that can be achieved on the given area of silicon. However, reductions in gate length can exacerbate many of the problems associated with fabrication of transistors. Although n-channel devices are particularly sensitive to the so-called short-channel effects (“SCE”) that can result from very short channel lengths, SCE also become a predominant problem in p-channel devices whenever L
eff
drops below approximately 0.8 &mgr;m.
While in operation, short-channel transistors that have heavily doped source and drain regions arranged laterally adjacent the gate conductor often experience a problem known as punchthrough, which can lead to an undesirable increase in the subthreshold current, I
Dst
. Punchthrough can occur when the reverse-bias voltage on the drain is increased, leading to a widening of the drain depletion region. The drain may eventually merge into the source region, thereby reducing the potential energy barrier of the source-to-body junction. Consequently, more majority carriers in the source region will have sufficient energy to overcome the barrier, causing an increased source-to-body current flow. Collection of some of this current by the drain leads to an increase in I
Dst
.
To prevent short-channel MOSFETS from entering punchthrough, the substrate doping may be increased to decrease the depletion-layer widths. For many long-channel devices, a single implant may serve as both a punchthrough stop and a V
T
adjust. In cases where a single implant is inadequate, such as in submicron MOSFETs, a second, deeper implant may be provided. This punchthrough dopant implant may be performed such that the peak concentration of the punchthrough dopant distribution is located at a depth near the bottom of the source and drain regions. This implant should also result in an increase, either immediately after implantation or as result of heat treatment induced migration, in the substrate background doping from the peak concentration of the punchthrough stopper implant to some point further down in the substrate beneath the depth of source/drain regions. Such additional doping advantageously reduces the lateral widening of the drain depletion region below the substrate surface.
Formation of a punchthrough dopant distribution, however, requires close control of the implant placement and dose within the channel region. Improper placement of the implant can result in unexpected threshold skew or ineffective punchthrough prevention. Unfortunately, even a properly placed punchthrough dopant distribution can migrate significantly during subsequent heat processing steps. Such migration is a particular problem with the boron often used for punchthrough preve
Fulford Jr. H. Jim
Gardner Mark I.
May Charles E.
Advanced Micro Devices , Inc.
Conley & Rose & Tayon P.C.
Crane Sara
Daffer Kevin L.
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