Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-05-05
2002-09-10
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S612000, C438S613000, C438S641000, C438S674000, C438S678000
Reexamination Certificate
active
06448171
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to microelectronic fabrications having formed therein terminal electrode structures. More particularly, the present invention relates to microelectronic fabrications having formed therein terminal electrode structures which provide enhanced passivation of the microelectronic fabrications and enhanced bondability to the terminal electrode structures.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
In conjunction with various means and configurations for interconnecting microelectronic fabrications of various varieties, it is common in the art of microelectronic fabrication to employ integral to individual microelectronic fabrications terminal electrode structures at locations within the individual microelectronic fabrications where the individual microelectronic fabrications are to be interconnected. Such terminal electrode structures are typically formed integral to the individual microelectronic fabrications while employing various metallurgy layers, which under certain circumstances may include solder interconnection layers, to which the various means and configurations for interconnecting the microelectronic fabrications may be connected.
While terminal electrode structures are thus desirable and clearly essential within the art of microelectronic fabrication for effectively providing electrical interconnections for various varieties of microelectronic fabrications which may be fabricated within the art of microelectronic fabrication, terminal electrode structures are nonetheless not entirely without problems in the art of microelectronic fabrication when fabricating microelectronic fabrications. In that regard, it is typically highly desirable within the art of microelectronic fabrication, but nonetheless not always readily achievable within the art of microelectronic fabrication, to provide within a microelectronic fabrication a terminal electrode structure which simultaneously provides enhanced passivation of microelectronic fabrication within which is formed the terminal electrode structure and enhanced bondability to the terminal electrode structure.
It is thus towards the goal of providing for use when fabricating a microelectronic fabrication a terminal electrode structure which simultaneously provides within the microelectronic fabrication an enhanced passivation of the microelectronic fabrication within which is formed the terminal electrode structure and enhanced bondability to the terminal electrode structure that the present invention is directed.
Various configurations and materials have been disclosed within the art of microelectronic fabrication for fabricating and testing, with desirable properties, terminal electrode structures within microelectronic fabrications.
For example, Agarwala et al., in U.S. Pat. No. 5,130,779, disclose: (1) a multi-layer solder layer terminal electrode structure with an enhanced aspect ratio for use within a microelectronic fabrication for directly interconnecting, with attenuated physical stress and strain, a pair of microelectronic substrates within the microelectronic fabrication; and (2) a method for forming the multi-layer solder layer terminal electrode structure with the enhanced aspect ratio for use within the microelectronic fabrication for directly interconnecting, with attenuated physical stress and strain, the pair of microelectronic substrates within the microelectronic fabrication. To realize the foregoing objects, the method for forming the multi-layer solder layer terminal electrode structure employs forming upon at least one terminal electrode solder layer employed within the multi-layer solder layer terminal electrode structure, prior to thermal reflow of the at least one terminal electrode solder layer: (1) a capping or encapsulant metal layer, or in the alternative; (2) a sidewall spacer layer, such that upon thermal reflow of the at least one terminal electrode solder layer the at least one terminal electrode solder layer is not susceptible to thermal reflow induced collapse.
In addition, Tsukamoto, in U.S. Pat. No. 5,640,052, discloses a terminal electrode structure for use when directly interconnecting a pair of microelectronic substrates within a microelectronic fabrication, where the terminal electrode structure provides for attenuated thermally induced physical stress and strain of the pair of microelectronic substrates with respect to the terminal electrode structure when directly interconnecting the pair of microelectronic substrates within the microelectronic fabrication while employing the terminal electrode structure. To realize the foregoing object, the terminal electrode structure employs a metal core layer having formed thereupon a solder terminal electrode layer which bridges to a pair of bond pads formed within the pair of microelectronic substrates, where the solder terminal electrode layer which bridges to the pair of bond pads formed within the pair of microelectronic substrates is formed with an hourglass shape.
Further, Strauss, in U.S. Pat. No. 5,719,449, disclose a flip chip integrated circuit microelectronic fabrication which employs therein a terminal electrode structure which provides for improved testability of the flip chip integrated circuit microelectronic fabrication. The flip chip integrated circuit microelectronic fabrication realizes the foregoing object by providing within the flip chip integrated circuit microelectronic fabrication a terminal metal layer which is fabricated to comprise a pair of interconnected bond pad layers, wherein: (1) one of the pair of interconnected bond pad layers serves as an electrical test bond pad layer terminal electrode structure within the flip chip integrated circuit microelectronic fabrication and has formed thereupon no additional metallurgy layers; and (2) a second of the pair of interconnected bond pad layers serves as an electrical interconnection bond pad layer and has formed thereupon a solder layer to provide an electrical interconnection terminal electrode structure within the flip chip integrated circuit microelectronic fabrication.
Finally, Wood et al., in U.S. Pat. No. 5,781,022, disclose an electrical test apparatus which provides for electrically testing an integrated circuit microelectronic fabrication die through contact of a probe which is integral to the electrical test apparatus with a bond pad terminal electrode structure which is integral to the integrated circuit microelectronic fabrication die, where neither the bond pad terminal electrode structure nor a passivation layer passivating a portion of the bond pad terminal electrode structure which is integral to the integrated circuit microelectronic fabrication die is damaged incident to electrically testing the integrated circuit microelectronic fabrication die with the electrical test apparatus. In order to realize the foregoing result, the electrical test apparatus employs the probe which comprises a nominally flat but nonetheless ridged probe surface which contacts the bond pad terminal electrode structure within the integrated circuit microelectronic fabrication die.
Desirable for use when fabricating microelectronic fabrications are additional terminal electrode structures which simultaneously provide within a microelectronic fabrication enhanced passivation of a microelectronic fabrication within which is formed the terminal electrode structure and enhanced bondability to the terminal electrode structure.
It is towards the foregoing objects that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a terminal electrode structure for use within a microelectronic fabrication, and a method for fabricating the terminal electrode structure for use within the microelectronic fabrication.
A second object of the present invention is to provide
Wang Tsing-Chow
Wu Te-Sung
Aptos Corporation
Nguyen Ha Tran
Tung & Associates
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