Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-01-29
2002-03-19
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S339000
Reexamination Certificate
active
06359307
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically to an improved fabrication process for making semiconductor memory devices.
BACKGROUND ART
In general, memory devices such as a Flash electrically erasable programmable read only memory (EEPROM) are known. EEPROMs are a class of nonvolatile memory devices that are programmed by hot electron injection and erased by Fowler-Nordheim tunneling.
Each memory cell is formed on a semiconductor substrate (i.e., a silicon die or chip), having a heavily doped drain region and a source region embedded therein. The source region further contains a lightly doped deeply diffused region and a more heavily doped, shallow diffused region embedded into the substrate. A channel region separates the drain region and the source region. The memory cell further includes a multi-layer structure, commonly referred to as a “stacked gate” structure or word line. The stacked gate structures typically include: a thin gate dielectric or tunnel oxide layer formed on the surface of a substrate overlying the channel region; a polysilicon floating gate overlying the tunnel oxide; an interpoly dielectric overlying the floating gate; and a polysilicon control gate overlying the interpoly dielectric layer. Additional layers, such as a silicide layer (disposed on the control gate), a poly cap layer (disposed on the silicide layer), and a silicon oxynitride layer (disposed on the poly cap layer) may be formed over the control gate. A plurality of Flash EEPROM cells may be formed on a single substrate.
The process of forming Flash EEPROM cells is well known and widely practiced throughout the semiconductor industry. After the formation of the memory cells, electrical connections, commonly known as “contacts”, must be made to connect the stack gated structure, the source region and the drain regions to other parts of the chip. The contact process starts with the formation of sidewall spacers around the stacked gate structures of each memory cell. An etch stop layer, typically a silicon nitride material, is then formed over the entire substrate, including the stacked gate structures, using conventional techniques, such as chemical vapor deposition (CVD). A dielectric layer, generally of oxide, is then deposited over the etch stop layer, and a layer of photoresist is placed over the dielectric layer and photolithographically processed to form the pattern of contact openings. An anisotropic oxide etch is then used to etch out portions of the dielectric layer to form source and drain contact openings in the dielectric layer. The contact openings stop at the etch stop layer. A further etch is then used to remove the etch stop layer so that the source and drain contact openings reach the source and drain region, respectively. The photoresist is then stripped. A conductive material, such as tungsten, is then deposited over the dielectric layer filling the source and drain contact openings. The substrate is then subjected to a chemical-mechanical polishing (CMP) process which removes the conductive material above the dielectric layer to form so-called “self-aligned contacts”. A layer of conductive material, such as tungsten, is then deposited over the dielectric layer and the contacts. The conductive layer is patterned to form interconnection lines to selectively connect to the contacts. The spacing between the interconnection lines are then filled with a dielectric material. The dielectric material above the interconnection lines is then planarized using for example, chemical-mechanical polishing (CMP) techniques.
One of the problems associated with the conventional self-aligned contact process is that it requires two separate metallization steps: one to fill the contact openings to form the contacts and the other to form the interconnection lines above the contacts. The other problem associated with the conventional self-aligned contact process is that it requires two planarization steps: one to planarize the dielectric layer to form the contacts, and the other to planarize the dielectric layer formed above the interconnection lines. Each additional metallization or planarization step adversely increases cycle time and process complexity and also introduces particles and defects, resulting in an increase in cost and yield loss.
A solution, which would reduce the number of process steps in forming self-aligned contacts and maintain the device performance has long been sought, but has eluded those skilled in the art.
DISCLOSURE OF THE INVENTION
The present invention provides an improved method for making semiconductor devices.
The present invention provides an improved method for making semiconductor devices that results in a reduction in cycle time, cost and yield loss.
The present invention further provides a method for forming self-aligned contacts using a dual damascene technique that results in a reduction in the number of process steps.
The present invention provides a method for forming self-aligned contacts which eliminates one metallization step and one planarization step by forming the contacts and the channels at the same time.
The present invention still further provides a method for forming a contact and a channel in a dielectric layer over a region on a semiconductor substrate. The contact is selfaligned. The contact and channel are formed by (1) forming a contact opening in the dielectric layer to expose a portion of the region on the semiconductor substrate, (2) forming a channel opening in the dielectric layer, wherein the channel opening encompasses the contact opening, and (3) filling the contact opening and the channel opening with a conductive material to form a contact and a channel, respectively.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5553018 (1996-09-01), Wang et al.
patent: 5776811 (1998-07-01), Wang et al.
patent: 6136649 (2000-10-01), Hui et al.
patent: 6242332 (2001-06-01), Cho et al.
Kinoshita Hiroyuki
Sahota Kashmir
Sun Yu
Wang Fei
Yang Wenge
Advanced Micro Devices , Inc.
Ishimaru Mikio
Le Bau T
Nelms David
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