Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-02-08
2002-01-15
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S636000, C438S637000, C438S706000, C438S710000, C438S725000, C134S001200
Reexamination Certificate
active
06339019
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device having a multilevel interconnection structure.
Due to a higher integration degree, higher density, and higher operation speed of LSIs (Large Scale Integrated circuits) and the versatility of the LSIs, multilevel interconnection formation is an indispensable technique not only in logic devices but also in large-scale memory elements. The multilevel structure decreases the interconnection area substantially to prevent an increase in chip size, and shortens the average interconnection length to suppress delay in operation speed caused by the interconnection resistance.
In this multilevel interconnection technique, it is important to reliably connect wiring layers to each other. Particularly, the connecting technique at many small through hole portions in super LSIs is important. When aluminum is used as the wiring material, an oxide film always exists on the surface of the aluminum film. Hence, when forming a plug to be connected to a lower aluminum interconnection in a through hole, the native oxide on the aluminum interconnection exposed on the bottom surface of the through hole must be removed.
When connecting aluminum multilevel interconnections to each other through a through hole, first, as shown in
FIG. 3A
, a predetermined element (not shown), a wiring layer (not shown) to be placed on the element, and the like are formed on a semiconductor substrate
300
, and an interlevel insulating film
301
is formed to cover the surface of the semiconductor substrate
300
. Then, a lower interconnection
302
made of aluminum is formed on the interlevel insulating film
301
.
As shown in
FIG. 3B
, an interlevel insulating film
303
is formed on the interlevel insulating film
301
including the lower interconnection
302
, and a resist pattern
304
having an opening is formed on the interlevel insulating film
303
formed on the lower interconnection
302
. As shown in
FIG. 3C
, by using the resist pattern
304
as a mask, the interlevel insulating film
303
is selectively etched by dry etching using a fluorine-based gas in a dry etching unit, thereby forming a through hole
305
.
The semiconductor substrate
300
is extracted from the dry etching unit and exposed to a plasma using oxygen gas in an ashing unit to remove the resist pattern
304
, as shown in FIG.
3
D. Consecutively, the substrate
300
is unloaded from the ashing unit, and the residual resist which was not removed by the ashing process is removed by a chemical solution process of dipping the substrate
300
in an amine-based solvent. Then, the native oxide on the lower interconnection
302
exposed to the bottom surface of the through hole
305
is removed by a cleaning process using an acid.
Tungsten is selectively deposited to form a plug
306
to fill the through hole
305
, as shown in FIG.
3
E. Then, as shown in
FIG. 3F
, an upper interconnection
307
to be connected to the plug
306
is formed on the plug
306
and the interlevel insulating film
303
around the plug
306
, so that a multilevel interconnection structure in which the lower and upper interconnections
302
and
307
are connected to each other through the plug
306
is formed.
In the conventional method, although the native oxide film on the lower interconnection
302
on the bottom surface of the through hole
305
is removed, the lower and upper interconnections
302
and
307
are not electrically connected at all in some cases. This is because a defect occurs in connection made through the through hole
305
, causing a conduction defect between the lower interconnection
302
and plug
306
.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device manufacturing method in which a connection failure between wiring layers is suppressed.
In order to achieve the above object, according to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the first step of forming a lower interconnection on a semiconductor substrate through a first insulating film, the second step of forming a second insulating film on the semiconductor substrate including the lower interconnection, the third step of forming a through hole in the second insulating film to reach the lower interconnection, the fourth step of etching, after the third step is ended, a surface of the lower interconnection including a side surface thereof exposed to a bottom portion of the through hole without exposing the semiconductor substrate to the atmosphere, the fifth step of forming a plug made of a conductive material in the through hole, and the sixth step of forming an upper interconnection to be connected to the plug on the second insulating film.
REFERENCES:
patent: 5866484 (1999-02-01), Muto
patent: 5904154 (1999-05-01), Chien et al.
patent: 5981374 (1999-11-01), Dalal et al.
patent: 62-24951 (1987-10-01), None
patent: 4-286327 (1992-10-01), None
patent: 4-337633 (1992-11-01), None
patent: 5-102108 (1993-04-01), None
patent: 6-244182 (1994-09-01), None
patent: 8-107144 (1996-04-01), None
patent: 63-245926 (1998-10-01), None
Foley & Lardner
Nguyen Ha Tran
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