Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-02-01
2002-09-24
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S239000, C365S240000, C365S189120
Reexamination Certificate
active
06456552
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to dynamic registers. More particularly, the invention relates to a method and a system for refreshing a dynamic register included in a high-speed communication integrated circuit while the integrated circuit is undergoing low frequency testing such as scan testing.
2. Description of Related Art
In a Gigabit Ethernet communication system that conforms to the IEEE 802.3ab (also termed 1000 BASE-T) standard, gigabit transceivers are connected via four Category 5 twisted pairs of copper cables. Symbol data are transmitted at the rate of 250 megabits per second (Mbps) on each twisted pair of copper cable.
A Gigabit Ethernet transceiver includes a larger number of adaptive filters, which in turn require a large number of registers. The registers operate at the clock rate of 125 megahertz (MHz). Dynamic registers are preferred over static registers due to their low power consumption and faster operating speed. A dynamic register consumes only about half the power consumed by a static register. Thus, the requirements of low power consumption and high operating speed of the Gigabit Ethernet transceiver necessitate the use of dynamic registers instead of static registers in most of the adaptive filters included in the Gigabit Ethernet transceiver. However, a dynamic register would lose its contents if it is operated at low clock rate.
The fact that dynamic registers lose their data contents when they are operated at low clock rate pose a problem in low clock rate testing such as scan testing of a chip. Scan testing is performed at production time to sort out the defective chips from a batch of chips. Structure allowing a chip to operate in scan mode is included in the design of the chip. In the scan mode, all the registers in the chip are connected in chain to form a long shift register. The path that connects the registers together is called the scan path, and is determined based on layout efficiency. The scan testing is as follows. First, the chip is reset. Then it operates normally with a deterministic input data. The normal operation is then stopped. The chip is switched to scan mode. The data inside the chip are shifted out. This data is called the signature of the chip. A test machine compares this signature with an expected output pattern (obtained by simulation of a good chip). If there is a match, then the chip is good. Otherwise, the chip has a defect. Scan testing is performed at low clock rate, thus cannot be performed satisfactorily with dynamic registers.
Thus, there is a need for a method and a system for refreshing a dynamic register included in an integrated circuit while the integrated circuit is undergoing low clock rate testing.
SUMMARY OF THE INVENTION
The present invention provides a method for refreshing data in a circuit element included in a dynamic register. A static loop is coupled to the circuit element as a feedback path from the output terminal to the input terminal of the circuit element. A control signal is provided to the static loop. The static loop is activated via the control signal to refresh the data in the circuit element.
The present invention provides a system for refreshing a dynamic register. The dynamic register includes a first transmission gate, a first inverter, a second transmission gate and a second inverter connected in series. The first and second transmission gates operate in accordance with complementary clock signals. A first static loop is coupled to the first inverter as a feedback path from the output terminal of the first inverter to the input terminal of the first inverter. The first static loop is activated or deactivated by a control signal. When activated, the first static loop refreshes the first inverter. A second static loop is coupled to the second inverter as a feedback path from the output terminal to the input terminal of the second inverter. The second static loop is activated or deactivated by the control signal. When activated, the second static loop refreshes the second inverter.
REFERENCES:
patent: 5008618 (1991-04-01), Van Der Star
patent: 5912859 (1999-06-01), Wuidart
IEEE, “Supplement to Carrier Sense Multiple Access With Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications—Physical Layer Parameters and Specifications for 1000 Mb/s Operation Over 4-Pair of Category 5 Balanced Copper Cabling, Type 1000BASE-T,” Information Technology—Telecommunications and Information Exchange Between Systems—Local and Metropolitan Area Networks—Specific Requirements—; 1999; 140 pages; IEEE Std 802.3ab (Supplement to IEEE Std 802.3 1998 Edition); IEEE, NY.
Broadcom Corporation
McAndrews Held & Malloy Ltd.
LandOfFree
Dynamic register with low clock rate testing capability does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dynamic register with low clock rate testing capability, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic register with low clock rate testing capability will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2867392