Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-04-10
2002-09-10
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S151000, C257S347000, C257S350000
Reexamination Certificate
active
06448116
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin film transistor display and a method of fabricating the same.
2. Description of the Prior Art
A thin film transistor display, such as a thin film transistor liquid crystal display (TFT-LCD), utilizes a lot of thin film transistors are arranged in a matrix as switches for driving liquid crystal molecules to produce brilliant images after co-operating with other elements such as capacitors and bonding pads. The advantages of the TFT-LCD include the portability, low power consumption, and low radiation. Therefore, the TFT-LCD is widely used in various portable products, such as notebooks, personal data assistants (PDA), etc. Moreover, the TFT-LCD replaces the CRT monitor in desktop computers gradually.
Please refer to
FIG. 1A
to
FIG. 1H
of schematic diagrams of a prior art method for fabricating a transistor of a TFT-LCD
10
. In the prior art, the transistor of the TFT-LCD
10
is formed on the surface of a glass substrate
12
. As shown in
FIG. 1A
, an aluminum (Al) layer
14
and a cap layer
16
are first deposited on the substrate
12
, respectively. Next, the Al layer
14
and the cap layer
16
are patterned by a first photo-etching process (PEP) to form a gate electrode.
Then, as shown in
FIG. 1B
, an insulating layer
18
, an amorphous silicon layer
20
, and a doped amorphous silicon layer
22
are deposited on the glass substrate
12
. As shown in
FIG. 1C
, a second photo-etching process is used to remove the portion of the doped amorphous silicon layer
22
and the amorphous silicon layer
20
outside the transistor area
24
. The insulating layer
18
is then exposed outside the transistor area
24
. As shown in
FIG. 1D
, a metal layer
26
is deposited on the glass substrate
12
. As shown in
FIG. 1E
, a third PEP is performed to pattern the metal layer
26
. Further, the doped amorphous silicon layer
22
is etched by using the metal layer
26
as a hard mask, the remaining doped amorphous silicon layer
22
and the metal layer
26
are used to form a source metal layer
28
and a drain metal layer
30
, respectively.
As shown in
FIG. 1F
, after the third PEP, a passivation layer
32
is deposited on the glass substrate
12
. Then, as shown in
FIG. 1G
, a fourth PEP process is performed to define the pattern of the passivation layer
32
and form a drain opening
34
above the drain metal layer
30
. Next, an indium tin oxide (ITO) layer
36
is deposited on the glass substrate
12
and fills in the drain opening
34
. Finally, as shown in
FIG. 1H
, a fifth PEP is!performed to form the pattern of the ITO layer
36
so that the drain metal layer
30
is electrically connected to a display region (not shown). The transistors are used to control the brightness of the TFT-LCD
10
.
The prior art method of fabricating the TFT-LCD
10
requires at least five photo-etching processes to form a transistor. The method is complicated, expensive, and time-consuming, resulting in a low yield of the TFT-LCD. Besides, each TFT-LCD includes many other electronic components, and these components will be affected when the yield of the TFT-LCD is low. Thus, the fabrication of the related electronic components must be integrated into a single process for cost-saving and make the TFT-LCD can compete with the low-cost CRT monitors.
SUMMARY
It is therefore a primary objective of the present invention to provide a new method of fabricating a thin film transistor display to solve the above-mentioned problem.
In a preferred embodiment, the present invention provides a method for fabricating a thin film transistor display. The thin film transistor display is fabricated on a substrate having a first region and a second region. The first region comprises a transistor area for the formation of a transistor, and the second region comprises a pad area for the formation of a pad. A first metal layer is deposited on the substrate and then patterned to form a gate electrode in the transistor area and a pad electrode in the pad area. Then, a first insulating layer is formed and patterned. The first insulating layer includes a pad opening formed in the pad area to expose the pad electrode. Further, a second insulating layer, a semiconductor layer, a doped silicon conductive layer, and a second metal layer are deposited on the first insulating layer. A channel area is defined in the transistor area, and then, removing portions of the second metal layer and the doped silicon layer positioned (1) outside the transistor area and (2) within the channel area. The remaining second metal layer forms a source metal layer and a drain metal layer at the transistor area. The source and drain metal layers are separated by the channel area, and the semiconductor layer is exposed outside the transistor area. Further, a passivation layer is deposited and patterned on the substrate. The portion of the passivation layer outside the first region is removed to expose the semiconductor layer outside the first region. Finally, by using the passivation layer as an etching mask, the semiconductor layer and the second insulating layer unprotected by the passivation layer is removed. The first insulating layer is therefore exposed outside the first region, and the pad electrode is exposed in the pad opening.
It is an advantage of the present invention that a method of fabricating a thin film transistor display can produce different kinds of capacitors as well as reduce the resistance of both transistors and capacitors under the same process condition.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
REFERENCES:
patent: 5466617 (1995-11-01), Shannon
patent: 5705413 (1998-01-01), Harkin et al.
patent: 5798534 (1998-08-01), Young
patent: 6207480 (2001-03-01), Cha et al.
Au Optronics Corp.
Hsu Winston
Picardat Kevin M.
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