Semiconductor memory device with a refresh function

Details Semiconductor memory device with a refresh function Semiconductor memory device with a refresh function

2001-03-23

2002-09-03

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S194000

Reexamination Certificate

active

06445637

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a dynamic random access memory (DRAM) which has a refresh function.
2. Description of the Related Art
A conventional art will now be described with reference to the drawings. A dynamic random access memory (DRAM) is a volatile memory for storing data in memory cell capacitor (memory cell capacity).
FIG. 4A
conceptually shows the structure of the periphery of the memory cells of the DRAM. A pair of digit lines D and DB is provided for a sense amplifier SA. A memory cell MC is provided at the intersection of the digit lines D and DB and a word line WL.
The memory cell MC comprises a memory cell capacitor Cm and a memory cell transistor Tm. The level of the counter electrode of the memory cell capacitor (memory cell capacitor counter electrode level) HVCD is applied to one of the electrodes of the memory cell capacitor Cm. The other electrode is connected to the source of the memory cell transistor Tm. The gate of the memory cell transistor Tm is connected to the word line WL, and the drain of the memory cell transistor Tm is connected to the digit line D or DB.
In order to prevent the data stored in the memory cell capacitor Cm (hereinafter referred to as memory cell data) from being lost, a refresh operation which is peculiar to the DRAM is required. The refresh operation drives the word line WL to select the memory cell MC. Then, the sense amplifier SA amplifies the memory cell data which has been read from the memory cell MC to the digit lines, and the data is then written in the same memory cell MC.
The refresh operation will now be explained with reference to the timing chart of FIG.
4
B. When an internal RASB signal, which is described below, is changed from a high level to a low level, the word line WL specified by the address (not shown) at that time is selected, and is driven to a high level. When the word line WL is selected, the memory cell transistor Tm is turned on, and therefore the memory cell data which is stored in the memory cell capacitor Cm appears on the digit line D.
The initial level (electric potential) of the digit lines D and DB is the same as the memory cell capacitor counter electrode level HVCD. The level of the digit line varies depending on the electric charge stored in the memory cell capacitor Cm. That is, when the word line WL is selected, the electric potential Vcell of the memory cell data stored in the memory cell capacitor Cm is determined based on the ratio of the capacity of the digit line D to the memory cell capacitor Cm. When the memory cell data is at a high level, the level of the digit line D is higher than the memory cell capacitor counter electrode level. The level of the digit line DB is maintained at the memory cell capacitor counter electrode level.
Subsequently, the difference in electric potential between the digit lines D and DB is amplified, and the RASB signal is reset from a low level to a high level. Then, the word line WL is driven to a low level, and therefore the memory cell transistor Tm is turned off. Thus, the data on the digit line, which had been amplified until the word line WL was started to be driven at a low level, is returned to and stored in the memory cell capacitor Cm.
This is the refresh operation to restore the memory cell data. The operation for storing the data into the memory cell capacitor Cm is termed “restore”, and the level of data given to the memory cell capacitor Cm is termed a “restore level”. When the restore operation is insufficient and the restore level is low, the time of holding (maintaining) the data in the memory cell is shortened. Thus, the maintenance of the memory cell data is degraded. As the time for which the RASB signal is maintained at a low level is lengthened, the time for which the word line has been selected is lengthened, the restore operation becomes sufficient, and the restore level is satisfactory. The time for which the RASB signal is maintained at a low level is termed a tRAS period.
There are two kinds of refresh operations. One is a CBR refresh operation, and the other is a CBR self-refresh operation (hereinafter referred to as self refresh). The CBR is an abbreviation of “CAS Before RAS”, and is derived from the entry to the refresh operation in response to an external column address strobe signal CAS before the input of an external row address strobe signal RAS when the DRAMs of FP (Fast Page) or EDO (Extended Data Out) are used. However, since the synchronous DRAM (SDRAM) provides command control based on a clock, the CBR refresh operation is not significant at present.
In the CBR refresh operation, on receiving an externally input command, an internal YRF signal, which is described below, is increased to a high level by one shot (one pulse) as shown in FIG.
5
. This is a trigger to conduct the refresh. In the self-refresh, the YRF signal repeats shots regardless of the external input. Thus, the refresh operation is automatically conducted. The details of this operation will be discussed below. Although the CBR refresh operation and the self-refresh operation are different only in that the YRF signal is produced by the external signal in the CBR refresh operation and the YRF signal is automatically and internally produced in the self-refresh operation, the operations are identical in that the YRF signal controls the internal refresh operation.
FIG. 5
shows a conventional circuit for producing the internal RASB signal in the refresh operation. This circuit comprises NOR (negative OR, or not OR) gates
71
and
72
. The output from the NOR gate
71
is connected to one of the inputs of the NOR gate
72
, and the output from the NOR gate
72
is connected to one of the inputs of the NOR gate
71
. The YRF signal is applied to the other input of the NOR gate
71
, and an RTO signal, which is described below, is applied to the other input to the NOR gate
72
. The RTO signal is internally produced to deactivate the word line.
FIG. 6
shows the waveforms of the YRF signal, the RTO signal, the RASB signal, and a SRS signal which is the entry signal for the self-refresh mode. The SRS signal is at a high level only when in the self-refresh operation, and defines the entry to and the exit from the self-refresh operation. As described above, the YRF signal is a one-shot signal at a high level which is produced by the external command in the CBR refresh operation and which is automatically and internally produced in the self-refresh operation. This YRF signal determines the following refresh operation.
The RTO signal deactivates the word line. When the RASB signal is increased to a high level, the RTO signal is reduced to a low level with a short delay (several nanoseconds) after the rising of the RASB signal. Then, several nanoseconds after the RASB signal has been reduced to a low level to complete the sense operation, the RTO signal is increased to a high level. As shown in
FIG. 5
, the RASB signal is produced from the YRF signal and the RTO signal, and defines the time period for which the word line has been selected. For normal initial conditions, the SRS signal is at a low level, the YRF signal is at a low level, the RTO signal is at a low level, the RASB signal is at a low level, and the output from the NOR gate
72
is at a low level.
The operation of the circuit shown in
FIG. 5
will now be-explained with reference to the timing chart of FIG.
6
. In the CBR refresh operation, the YRF signal is increased to a high level by the external command. Then, the RASB signal which is the output from the NOR gate
71
is reduced to a low level. Further, the output from the NOR gate
72
is reduced to a low level. Thereafter, the YRF signal is reduced to a low level. Then, the RTO signal is increased to a high level with the delay of several nanoseconds from the reduction of the YRF signal. Then, the output from the NOR gate
72
is reduced to a low level. Then, the RASB signal, which is the output from the NOR gate
71
, is increa

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