Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-04-10
2002-03-12
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S302000, C438S592000, C438S683000
Reexamination Certificate
active
06355512
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an insulated gate transistor (TFT) formed on an insulating surface of, e.g., an insulating material such as glass or a material which an insulating film such as a silicon oxide is formed on a silicon wafer, and to a producing method therefore. The invention particularly suitable for a TFT formed on a glass substrate having a glass transition point (a strain temperature or a strain point) of 750° C. or lower. A semiconductor device of the invention is used in an active matrix of a liquid crystal display, a driving circuit of an image sensor, or a three dimensional integrated circuit.
2. Description of the Related Art
Conventionally, it is commonly known that TFTs (thin film transistors) are formed to drive an active matrix type liquid crystal display device, an image sensor, or the like. Recently, For high speed operation, the crystalline silicon TFT having a higher electric field mobility have been developed to replace the amorphous silicon TFT having an amorphous silicon active layer. Further, to realize high characteristics, there is required a structure in which to reduce the sheet resistance of the source and drain, they are formed with silicide as in the semiconductor integrated circuit manufacturing technology. As for the silicide structure, refer to H. Kaneko et al., IEEE Trans. Electron Devices, ED-33, 1702 (1986), for instance.
However, in contrast to the known semiconductor integrated circuit manufacturing technology, the TFT manufacturing technology still has many problems to be solved. In particular, there is a strong restriction that it cannot form a minute pattern, because devices are formed on an insulating surface and reactive ion anisotropic etching cannot be fully effected.
FIGS. 6A
to
6
G show presently used typical processes for producing a silicide structure. A base film
602
is formed on a substrate (glass substrate or silicon wafer)
601
. An active layer
603
is formed thereon with crystalline silicon. An insulating film
604
is formed on the active layer
603
with a material such as silicon oxide. (
FIG. 6A
)
A gate electrode
605
is formed with polycrystalline silicon (doped with an impurity such as phosphorus), tantalum, titanium, aluminum, etc. Impurity regions
606
are formed in the active layer
603
by introducing an impurity element (phosphorus or boron) by ion doping or the like in a self-alignment using the gate electrode
605
as a mask. The region of the active layer
603
which is located under the gate electrode and into which the impurity is not introduced becomes a channel forming region. (
FIG. 6B
)
An insulating film
607
of silicon oxide or the like is formed by plasma chemical vapor deposition (plasma CVD) or atmospheric pressure CVD (APCVD). (
FIG. 6C
)
By anisotropically etching the film
607
, side walls
608
are formed adjacent to the side surfaces of the gate electrode
605
. (
FIG. 6D
)
A metal film
609
of titanium, chromium, tungsten, molybdenum, or the like is formed on the entire surface to form a silicide thereof. (
FIG. 6E
) Silicide regions
610
are formed by causing the metal film to react with the impurity regions
606
. Since silicide is not formed in the portions (width: x) of the impurity regions
606
under the side walls
608
, those portions become ordinary source and drain regions
611
. (
FIG. 6F
)
After an insulating film
612
is formed, contact holes for the source and drain regions
611
are formed through the interlayer insulating film
612
, and then wiring electrodes
613
connecting to the source and drain
611
are formed with a metal material such as aluminum. (
FIG. 6G
)
The above process uses the silicide forming process itself of the conventional semiconductor integrated circuit manufacturing technology, and therefore includes a step that is hard to apply to the process of producing TFTs on a glass substrate, and a step that is not favorable in productivity.
Firstly, the surface of the active layer needs to be etched after doping. It is known that a thinner active layer of a TFT provides better characteristic. Thus, in forming the side walls
608
in
FIG. 6D
, it is necessary to prevent overetching of the active layer
603
. However, while a thickness of the active layer
603
should be 1,500 Å or less, more preferably 800 Å or less, the insulating film
607
for forming the side walls
608
should be approximately as thick as the gate electrode
605
and has 3,000 to 8,000 Å in thickness, so that overetching cannot be prevented. Also, the active layer
603
doped with an impurity (i.e., doped silicon) is etched easily in comparison with intrinsic silicon. Thus, under the ordinary conditions, in forming the side walls
608
, the active layer
603
is greatly etched or cannot be etched with good reproducibility.
Secondly, it is difficult to form the side walls
608
. The insulating film
607
is as thick as 0.5 to 2 &mgr;m. Since usually the thickness of the base film
602
formed on the substrate
601
is 1,000 to 3,000 Å, it frequently occurs that this etching is erroneously performed to etch the base film
602
to thereby expose the substrate
601
. This results in a reduction of the yield. Particularly, since the glass substrate used to produce TFTs includes many elements that are harmful to a silicon semiconductor, the overetching needs to be prevented.
It is also difficult to form the side walls
608
with uniform widths. Because of the use of a substrate having an insulating surface, rather than a silicon substrate used in producing a semiconductor integrated circuit, it is difficult to finely control plasma during plasma dry etching such as reactive Ion etching (RIE).
SUMMARY OF THE INVENTION
An object of the present invention is to solve the above problems and to provide a method for producing a silicide structure by a simplified process. In the invention, silicide is formed without using the side walls. That is, the fundamental concept of the invention is that doping for the source and drain regions is performed after a metal film for forming silicide is formed.
According to the invention, a semiconductor device producing method comprises the steps of: (A) forming a semiconductor active layer on an insulating surface, forming an insulating film on the semiconductor active layer, and forming a gate electrode material film on the insulating film using an anodizable material; (B) forming a gate electrode by selectively providing a mask film on the gate electrode material film and etching the gate electrode material film using the mask film; (C) forming a first porous anodic oxide mainly on a side surface of the gate electrode by supplying a current to the gate electrode in an electrolytic solution; (D) removing the mask film; (E) forming a second barrier type anodic oxide on top and side surfaces of the gate electrode by supplying a current to the gate electrode in an electrolytic solution; (F) exposing a surface of a portion of the semiconductor active layer by removing (etching) a portion of the insulating film using the first anodic oxide as a mask, and at the same time forming a gate insulating film; (G) selectively removing the first anodic oxide; (H) forming a silicide forming metal film to cover the gate electrode and the gate insulating film; (I) selectively introducing an N-type or P-type impurity element into the semiconductor active layer through the metal film by using the gate electrode and the gate insulating film as masks; (J) selectively forming a silicide region in the semiconductor active layer by causing the metal film to selectively react with the semiconductor active layer; and (K) removing a portion of the metal film that has not reacted in step (J).
Among the above steps, while the order of steps (A) to (H) cannot be changed, the order of steps (I) to (K) can be changed. The following two processes are possible by properly combining steps (I) to (K):
First order: step (I)→step (J)→step (K)
Second order: step (J)→step (I)→step (
Takemura Yasuhiko
Yamazaki Shunpei
Booth Richard
Nixon & Peabody LLP
Robinson Eric J.
Semiconductor Energy Laboratory Co,. Ltd.
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