Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-03-17
2002-03-05
Kim, Hong (Department: 2751)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S134000, C711S109000, C711S100000, C711S219000, C711S132000, C711S144000
Reexamination Certificate
active
06353874
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to memory accesses and more particularly to a method and apparatus for controlling and caching memory read operations.
BACKGROUND OF THE INVENTION
As computing systems continue to evolve, numerous processing entities involved in a computing system may interact with numerous data storage devices. Thus, a particular memory client may require data from a plurality of different data storage devices included in the processing system. Typically, a bus structure interconnects the various memory clients and memory devices, or other data storage devices, where the bus structure provides the conduit for carrying control information and data between the data storage devices and the memory clients.
In operation, the client issues memory requests for all of the storage devices via the bus, where each of the data storage devices may require a different amount of time to respond to requests directed to that data storage device. For example, local memory may provide a rapid response time, whereas a read request that is forwarded through an accelerated graphics port (AGP) bus interface to a storage entity residing on the AGP bus may take a significantly larger amount of time. Most memory clients are designed such that it is desirable to have the responses to the memory requests provided to the client in the order in which the memory requests were initially issued.
In order to ensure that the ordering of the responses to the read requests issued by the client are provided in the proper order, some prior art systems employ circular buffers that include a read and write pointers. The write pointer is used to store incoming data generated in response to the memory read requests, whereas the read pointer is used to access the circular buffer to retrieve the data to be provided to the client. Flags are included in the circular buffer that indicate validity of the data at various locations within the circular buffer. When the read pointer detects that the segment of data corresponding to a memory read operation is valid, it retrieves this data from the circular buffer and provides it to the client. The write pointer is used in association with the read requests received to generate storage addresses in the circular buffer that are used to store the results of the read operations. By buffering data retrieved for read operations in the circular buffer, the ordering of the responses to the various read requests can be properly ordered.
In many cases, there is some coherency within a series of read requests. For example, the same data fetched during one request may be fetched again in the near future. Similarly, the minimum amount of data that is retrieved from memory may be a block of data where the client only requires a small portion of the block for each read request. However, subsequent requests by that client may correspond to additional portions of the larger block of data originally fetched. Prior art systems that ensure memory read response ordering did not provide any means for taking advantage of such coherency in read requests.
Therefore, a need exists for a method and apparatus for controlling memory read operations that provide a level of caching such that coherency within a series of read requests can be exploited to improve overall system efficiency.
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ATI International Srl
Kim Hong
Vedder Price Kaufman & Kammholz
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