Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-01
2002-09-17
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S059000, C257S061000, C257S327000, C257S333000, C257S337000, C257S338000, C257S346000, C257S347000, C438S217000, C438S276000, C438S289000, C438S291000
Reexamination Certificate
active
06452232
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a SOI structure and a manufacturing method thereof. More particularly, it relates to a semiconductor device which is formed on a SOI substrate having a high-concentration impurity diffusion region and can be applied to an integrated circuit operated by a low voltage, and a manufacturing method thereof.
2. Description of the Related Art
In recent years, a low voltage operation has been realized in a CMOS circuit, and in order to have a sufficient operational margin for realizing such a low voltage operation (Vdd<1.5 V) of the CMOS circuit, the threshold voltage (Vth) of a MOSFET constituting the CMOS circuit needs to be reduced to about ¼ or less of a power supply voltage (Vdd).
However, when the threshold voltage is reduced, the OFF leakage current of the MOSFET exponentially increases according to the following formulas:
Idoff=lox×10
−Vthis
lo≈2×10
−7
Amp/&mgr;m
S
=
ln
10
·
ⅆ
Vgs
ⅆ
(
ln
Ids
)
=
(
ln
10
)
·
kT
q
(
1
+
Cd
Cox
)
≈
90
mV
/
dec
where Idoff is a drain current in an OFF state (Vg=0), Io is a drain current when Vg=Vth, S is a gradient of a subthreshold (S factor), Cd is a depletion layer capacitance, and Cox is a gate capacitance.
It is found from these formulas that there is a trade-off relationship between the operating voltage of a transistor and the standby current of an LSI. Therefore, a MOSFET having a low threshold voltage causes a large standby current, and hence is not practical for a low voltage-, low power consumption-, and battery-operated LSI, and the like.
As a method of solving a problem of a trade-off relationship between the low threshold voltage and the OFF leakage current, it is thought to be effective to control the threshold voltage of the MOSFET in an operational state and a standby state: that is, in the operational state of a transistor, in order to realize the low voltage operation of the MOSFET, the threshold voltage is set at a low value, and in the OFF state, in order to reduce the OFF leakage current, the threshold voltage is set at a high value.
In this connection, in the case where the MOSFET is formed on a SOI substrate, there are several advantages such as a complete dielectric isolation, a latch-up-free, and the like. In particular, in the case of the MOSFET with a fully depleted SOI structure, since the whole channel region of a surface semiconductor layer is thin enough to be fully depleted, the Cd becomes O and the S factor can be reduced to 60 mV/dec at room temperature. This can reduce the OFF current. It is clear, however, that the trade-off relationship of the low threshold voltage is only shifted to low voltage.
Also, as an alternative method of controlling the threshold voltage, for example, a dynamic threshold MOS (hereinafter referred to as DTMOS) formed on a substrate having a SOI structure is proposed in IEEE (Trans. On Electron Devices, vol 44, no.3, p414-422, March 1997). The DTMOS has a structure, as shown in
FIG. 10
, in which a buried insulating film
31
and a surface semiconductor layer
32
are formed on a silicon substrate
30
and in which a gate electrode
33
, source/drain regions
32
a
, and a channel region
32
b
are formed on the surface semiconductor layer
32
. Also, the gate electrode
33
is electrically connected to the channel region
32
b
. This structure makes it possible to apply a voltage to the channel region
32
b
directly and to control the threshold voltage of the channel.
However, in the DTMOS, each transistor needs an additional contact between the channel region
32
b
and the gate electrode
33
because the channel region
32
b
is required to be connected directly to the gate electrode
33
. This causes a problem of increasing a layout area and complicating a manufacturing process. Additionally, this also causes a problem that the operating voltage Vdd needs to be much lower than the turn-on voltage (0.6 V) of a diode between the source and the substrate so as to avoid a leakage current, which restricts the application of the DTMOS.
Further, another example is a MOS type semiconductor device having the SOI structure shown in
FIG. 11
, which is disclosed in Japanese Patent Laid-Open No. 9-246562. This semiconductor device has a structure in which a gate electrode
43
, source and drain regions
41
,
42
, and a channel region
40
are formed on a surface semiconductor layer and in which there is provided a body contact region
44
adjacent to the source region
41
via a device isolating film
45
and a path
46
electrically connecting the channel region
40
to the body contact region
44
. This structure makes it possible to apply a voltage to the channel region
40
directly and hence to control the threshold voltage of the channel.
However, this structure has a path
46
connecting the channel region
40
to the body contact region
44
in the region surrounding the transistor and hence presents a problem that it needs a larger design area for the semiconductor device.
Further, still another example is the semiconductor device shown in
FIG. 12
which is disclosed in Japanese Patent Laid-Open No. 9-36246. In this semiconductor device, a buried insulating film
51
and a surface semiconductor layer
52
are formed on a silicon substrate
50
and a MOS transistor is formed on the surface semiconductor layer
52
and each channel region
53
of this MOS transistor is connected to a bias circuit
54
, whereby voltage is directly applied to the channel region
53
to control the threshold voltage of the channel.
However, this semiconductor device presents a problem that it needs a larger layout area as is the case with the other semiconductor device described above because each transistor needs to be connected to the bias circuit.
SUMMARY OF THE INVENTION
In according with one aspect of the present invention, there is provided a semiconductor device with a SOI structure comprising; a SOI substrate having a buried insulating film and a first conductivity type surface semiconductor layer on the buried insulating film; second conductivity type source and drain regions formed in the surface semiconductor layer; and a gate electrode formed over a first conductivity type channel region between the source and drain regions via a gate insulating film, wherein the source and drain regions are thinner than the surface semiconductor layer, and the channel region in the surface semiconductor layer has a first conductivity type high-concentration impurity diffusion region whose first conductivity type impurity concentration is higher than that in a surface of the channel region and which is adjacent to the buried insulating film.
In according with another aspect of the present invention, there is provided a method of manufacturing a semiconductor device with a SOI structure, said method comprising the steps of: i) forming a buried insulating film and a first conductivity type surface semiconductor layer over a substrate and forming a gate insulating film and a gate electrode over the surface semiconductor layer; ii) implanting second conductivity type impurity ions by using the gate electrode as a mask to form second conductivity type source and drain regions; and iii) implanting second conductivity type impurity ions more deeply by using the gate electrode as a mask to reduce the first conductivity type impurity concentration of the first conductivity type surface semiconductor layer under the second conductivity type source and drain regions, thereby forming a first conductivity type high-concentration impurity diffusion region which is a first conductivity type channel region between the second conductivity type source and drain regions and is adjacent to the buried insulating film, and whose first conductivity type impurity concentration is higher than that in a surface of the channel region.
REFERENC
Lee Eddie
Ortiz Edgardo
Sharp Kabushiki Kaisha
LandOfFree
Semiconductor device having SOI structure and manufacturing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having SOI structure and manufacturing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having SOI structure and manufacturing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2864660