Electrical computers and digital processing systems: memory – Storage accessing and control
Reexamination Certificate
2000-04-18
2002-03-26
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
C365S185080, C365S189011, C365S230010, C365S230030
Reexamination Certificate
active
06363454
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory systems and in particular to a memory system having multiple memory devices connected to memory controller by way of a common system bus, with the memory devices storing control parameters provided by the controller and used in carrying out memory operations.
2. Description of Related Art
Semiconductor memories having increased storage capacity have been developed. A typical memory system may include a single memory controller implemented on a single integrated circuit together with one or more memory devices, each of which is implemented on a single integrated circuit, having an array of memory cells. The memory controller and memory devices are typically connected by way of a bus so that the controller can issue memory read, program and erase commands to a selected one of the memory devices.
The storage capacity of such a memory system can be increased by adding additional memory devices to the system. Such memory devices are typically implemented to carry out memory operations, including read, program and erase operations in response to read commands accompanied by an address, program commands accompanied by an address and data to be programmed and erase commands. In order to carry out such memory operations, the memory devices typically include relatively complex control circuitry. This increased complexity increases the cost of the memory devices.
In addition, some semiconductor memories are designed to store control parameters in one form or another. Such control parameters may, for example, be used to precisely control the magnitude of the voltages applied to the memory cells during memory operations thereby optimizing such operations. Such control parameters may be stored using fusible links or using non-volatile memory cells. This approach further adds complexity and costs.
A memory system of the type having a memory controller and a plurality of memory devices, where the memory devices contain a minimal amount of complex circuitry would be desirable. By way of example, in a memory system embodied in a single computer card (PCMCIA or PC card), there is a single controller integrated circuit and several associated memory integrated circuits. Rather than duplicating the control logic in each of the memory circuits, it would be advantageous to locate the control circuits in the controller. Further, a memory capable of storing control parameters without the use of fusible links or non-volatile memory cells would be desirable. The present invention provides these and other advantages which will be readily apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.
FIG. 1
depicts a simplified conventional memory system which includes a host device
20
, an address decoder
22
and memory devices
24
A and
24
B. The host device
22
may be a microprocessor and the memory devices
24
A and
24
B may be separate memory integrated circuits. An address bus
26
is used to provide addresses to an address decoder
22
and to the memory devices
24
A and
24
B. The address decoder
22
has two outputs connected to enable inputs of the memory devices
24
A and
24
B. Typically, the most significant bit(s) of the address are provided on the bus
26
to the decoder
22
, with the remaining address bits being provided to each of the memory devices.
When memory is to be accessed, the processor
20
causes the address decoder
22
to decode the most significant bit(s) of the memory address placed on an address bus
26
. The decoder
22
will select one of the two memory devices
24
A and
24
B by generating either signal Sel
0
or Sel
1
. The selected memory device will respond to the address presented to it on the address bus and the deselected memory device, which is disabled, will not respond. Although not shown, a data bus is used to transfer data between the memory devices and the processor
20
, with only the selected device outputting data to the data bus during memory read operations.
The approach depicted in
FIG. 1
is sometimes referred to as radial device selection where each memory device has a separate select input. This approach works well when relatively few memory devices are employed and where access speed, particularly random access speed, is important. However, if a large number of memory devices are used so that large amounts of data can be stored, the requirement of separate select lines for each memory device results in large memory boards and a relatively large pin count for the control logic circuitry. Thus, unless access speed is critical and a large number of memory devices are used, the radial device selection approach of
FIG. 1
is not ideal.
FIG. 2
shows an alternative prior art device selection technique, sometimes referred to as serial selection. Again, a host device
28
is used which is connected to several memory devices
30
A,
30
B and
30
C by way of a system bus
32
. The memory devices
30
A,
30
B and
30
C are usually implemented as separate integrated circuits. The system bus
32
includes memory address and memory data and various control signals so that each of the memory devices
30
A,
30
B
30
C receives the same addresses, data and other signals. Each memory device is preassigned a unique address so that only one device will be accessed by the host device
28
during a memory operation. Typically, the memory devices
30
A,
30
B and
30
C are assigned addresses by way of jumper or switch settings represented by elements
34
A,
34
B and
34
C.
The
FIG. 2
approach requires that dedicated pins be provided on each of the integrated circuit memory devices
30
A,
30
B and
30
C to receive the jumper wires or switches for assigning the addresses. These pins increase the pin count for the integrated circuits thereby increasing the cost of the packaging for the devices and increasing the likelihood that there will be mechanical problems and manufacturing errors through soldering and the like. These extra pins are also subject to defects and increase the possibility of damage to the integrated circuits as a result of electrostatic discharge.
SUMMARY OF THE INVENTION
A memory system comprising a memory controller and a plurality of memory devices coupled to a common system bus. The memory controller is configured to issue memory program instructions, memory read instructions, memory erase instructions together with control parameters over the system bus to the memory devices. Each of the memory devices includes an array of non-volatile memory cells having control gate connected to common word lines, drains connected to common bit lines and sources connected to at least one source line.
The memory devices each further include a memory operation manager configured to receive the control parameters over the system bus and to transfer the control parameters to a plurality of volatile control registers. The operation manager is further configured to carry out the memory operations by applying operation voltages to the word, bit and source lines of the array, with at least one of the operation voltages being controlled by the control parameters. In a typical system, the control parameters originating from the memory controller to determine the magnitude and duration that the voltages are applied to the array. This feature permits, among other things, the memory operations to be controlled by the external memory controller so that the memory operations can be optimized. Further, the amount of control circuitry contained in each of the memory devices is minimized so as to reduce the manufacturing costs of the memory devices.
REFERENCES:
patent: 5392236 (1995-02-01), Hashimoto
patent: 5509134 (1996-04-01), Fandrich et al.
patent: 5517625 (1996-05-01), Takahashi
patent: 5602987 (1997-02-01), Harari et al.
patent: 5615159 (1997-03-01), Roohparvar
patent: 5619453 (1997-04-01), Roohparvar et al.
patent: 5627784 (1997-05-01), Roohparvar
patent: 5675540 (1997-10-
Chevallier Christophe J.
Lakhani Vinod C.
Norman Robert D.
Bataille Pierre-Michel
Kim Matthew
Schwegman Lundberg Woessner & Kluth P.A.
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