Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-07-18
2002-07-02
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S039000
Reexamination Certificate
active
06414514
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to the field of integrated circuits and their operation. More specifically, in one embodiment, the invention provides an improved logic device and method of its operation.
Logic devices and their methods of operation are well known to those of skill in the art. In particular, programmable logic devices have found wide application as a result of their combined low up-front cost and versatility to the user.
Altera's FLEX® and MAX® lines of programmable logic devices are among the most advanced and successful programmable logic devices in the industry. In the FLEX logic devices, a large matrix of logic elements is utilized. In a current commercial embodiment of such devices, each logic element includes a 4-input look-up table for performance of combinational logic and a register that provides for synchronous logic operation.
The logic elements are arranged in groups of, for example, eight logic elements to form larger logic array blocks (LABs). The LABs contain, among other things, a local interconnection structure. The local interconnections allow the outputs of the logic elements to be efficiently routed to other logic elements within a LAB. The various LABs are arranged on the device in a two dimensional array. The various LABs may be connected to each other and to pins of the device though continuous lines that run the entire length and width of the device.
The FLEX logic devices have met with substantial success and are considered pioneering in the area of programmable logic. While pioneering in the industry, certain limitations still remain. For example, it would be desirable to further increase the flexibility of the user and CAD software to program the device. In the presently available configurations, a particular signal may be blocked. That is, the signal cannot be routed out of a logic element or LAB because a path is not available. It is desirable to create a configuration in which blocked signals are minimized.
From the above, it is apparent that an improved logic device and method of its operation is desirable.
SUMMARY OF THE INVENTION
An improved logic device and method of operation is provided by virtue of the present invention. An aspect of the invention provides an improved logic element. The improved logic element performs routing functions as well as logic functions. Input signals of a logic element may be routed to one or more outputs of the logic element directly or after being operated upon by a logic function block.
In another aspect of the invention, additional routing flexibility is provided in a programmable logic device. The logic elements of a programmable logic device are arranged to form a Clos network. Although described herein with reference to columns and rows, it will be recognized that no horizontal or vertical meaning is intended. That is, the rows and columns may each be horizontally, vertically, or otherwise arranged. Any reference to rows and columns is intended only for ease of explanation of the preferred embodiment.
A plurality of logic elements are formed in rows and columns. Each column is fed by a set of column input signals, and each row provides a set of row output signals. Each of the logic elements in a row provide output signals that are combined to form a set of row output signals. Therefore, a grid with m rows and m columns, having logic elements with n outputs will have m sets of (m*n) outputs. Each column is provided with (m*n) inputs.
More than one plurality of logic elements of the arranged as described above may be combined with the row outputs of one being the column inputs to another. The plurality of logic elements may be oriented at about 90 degrees from each other providing for ease of routing. Three of more groups of logic elements combined in this manner form a Clos network. A Clos network ensures that a non-blocking path is available for each one-to-one mapping for the signals in the network.
A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings.
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Altera Corporation
Cho James H
Tokar Michael
Townsend and Townsend / and Crew LLP
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