Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-25
2002-03-05
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S173000, C257S174000, C257S487000, C257S356000, C257S357000, C257S360000, C257S546000, C257S378000
Reexamination Certificate
active
06353247
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a high voltage electrostatic discharge protection circuit, and more particularly to a high voltage electrostatic discharge protection circuit having a virtual N
30
region for increasing the distance between the base and collector of a parasitic bipolar junction transistor to ensure that its holding voltage is greater than its operation voltage, thereby preventing a problem of latch up.
2. Description of the Prior Art
In semiconductor industry, electrostatic discharge (ESD) is always a main reason to cause damages on ICs during manufacturing. For example, under an environment with higher relative humidity (RH), there will be several hundred, even several thousand, voltages of electrostatic charges detected when a person walks through a rug. In an environment with lower relative humidity, electrostatic charges will reach more than ten thousand voltages. When the rug or person bringing high voltage electrostatic charges contacts a chip, the electrostatic charges will be discharged toward the chip, causing irretrievable damages on the chip. To prevent chips from any damages caused by electrostatic charge discharge, various electrostatic discharge protection circuits have been developed. Typically, in the prior art, an on-chip electrostatic discharge protection circuit is designed between an internal circuit and each pad for protecting the internal circuit from damages.
Referring to
FIG. 1
, a structure of a conventional high voltage electrostatic discharge protection circuit is shown. In the conventional high voltage electrostatic discharge protection circuit, a high voltage N-well region
12
and a high voltage P-well region
14
adjacent to each other are formed in an N-type substrate
10
. A PMOS transistor
16
is formed on the high voltage N-well region
12
. The PMOS transistor
16
has its gate
18
and source
20
electrically connected to a high voltage V
DD
, together and its drain electrically connected to an input/output pad (I/P PAD)
23
.
The source
20
is constructed by a P
+
-type region
24
, a P-grad region
26
and a P-drift region
28
. The P-grade region
26
is beneath and sounding the P
+
-type region
24
. The P-drift region
28
is adjacent to the P-grade region
26
, partly under the gate
18
. Similarly, the drain
22
is constructed by a P
+
-type region
30
, a P-grade region
32
and a P-drift region
34
. The P-grade region
32
is beneath and surrounding the P
+
-type region
30
. The P-grade region
32
is beneath and surrounding the P
+
-type region
30
. The P-drift region
34
is adjacent to the P-grade region
32
, partly under the gate
18
. Furthermore, on the high voltage N-type well region
12
, there are an N
+
-base connection region
38
electrically connected to the high voltage V
DD
and a first isolation region
36
, wherein the source
20
and the N-base connection region
38
are adjacent to both sides of the first isolation region
36
.
Similarly, an NMOS transistor
42
is formed on the high voltage P-well region
14
. The NMOS transistor
42
has its gate
44
and source
46
electrically connected to ground V
ss
, together and its drain
48
electrically connected to the input/output pad
23
. The drain
48
is constructed by an N
+
-type region
50
, an N-grade region
52
and an N-drift region
54
. The N-grade region
52
is beneath and surrounding the N
+
-type region
50
. The N-type drift region
54
is adjacent to the N-grade region
52
, partly under the gate
42
. The source
46
is constructed by an N
+
-type region
56
, an N-grade region
58
and an N-drift region
60
. The N-grade region
58
is beneath and surrounding the N
+
-type region
56
. The drift region
60
is adjacent to the N-grade region
58
, partly under the gate
44
. Moreover, on the high voltage P-well region
14
, there are an P
+
-base connection region
64
electrically connected to the ground V
ss
, wherein the source
46
and the P
+
-base connection region
64
are adjacent to both sides of a second isolation region
62
.
Additionally, there is a third isolation region
40
is formed on the N-type substrate
10
and between the high voltage N-well region
12
and the high voltage P-well region
14
. In other words, the drain
22
of the PMOS transistor
16
and the drain
48
of the NMOS transistor
42
are located on both sides of the third isolation region
40
.
Due to the requirement of high voltage process, the P-well region
14
is formed with high resistance. Consequently, two parasitic bipolar junction transistors
66
,
68
shown in
FIG. 1
have a higher breakdown voltage (BV). Meanwhile, as shown in
FIG. 2
, after the input voltage of each parasitic bipolar junction transistors
66
,
68
reaches the trigging voltage Vtl (i.e., the two parasitic bipolarjunction transistors
66
,
68
are turned on), the input voltages speedily drops to a snapback voltage Sb, the current flowing through the two bipolar junction transistors
66
,
68
is greatly increased and then the input voltage is over an operation high voltage Vop. Since the P-well region
14
has higher resistance, the snapback voltage Sb is much lower than the operation high voltage Vop. Therefore, during a normal operation, a latch up problem will be caused to malfunction IC products once the electrostatic discharge protection circuit is electrically conducted.
SUMMARY OF THE INVENTION
In view of the above, the invention is to provide a high voltage electrostatic discharge protection circuit having a virtual N
+
region for adjusting the gain &bgr; of a parasitic bipolar junction transistor to ensure that its holding voltage is always greater than its operation voltage, by increasing the distance between the base and collector of the parasitic bipolar junction transistor, thereby preventing a problem of latch up.
The structure of the high voltage electrostatic discharge protection circuit is as follows. A high voltage N-well region is formed on the substrate. A high voltage P-well region is formed on the substrate and adjacent to the high voltage N-well region. A PMOS transistor is formed on the high voltage N-well region, having its gate and source electrically connected to a high voltage source, together and its drain electrically connected to an input/output terminal, wherein each of the drain and source is constructed by a P
+
-type region, a P-grade region located under and surrounding the P
+
type region and a P-drift region adjacent to the P-grade region, partly under the gate of the PMOS transistor. An N
+
-base connection region is formed on the high voltage N-well region and electrically connected to the high voltage source. A first isolation region is formed on the high voltage N-well region, having the source of the PMOS transistor and the N
+
-base connection region adjacent to both sides thereof. An NMOS transistor is formed on the high voltage P-well region, having its gate and source electrically connected to ground, together and its drain located on the junction of the high voltage P-well region and the high voltage N-well region, wherein each of the drain and the source is constructed by an N
+
-type region, an N-grade region located under and surrounding the N
+
-type region and an N-drift region adjacent to the N-grade region, partly under the gate of the NMOS transistor. A P
+
-base connection region is formed on the high voltage P-well region and electrically connected to the ground. A second isolation region is formed on the high voltage P-well region, having the source of the NMOS transistor and the P
+
-base connection region adjacent to both sides thereof. A virtual N
+
region is formed on the high voltage N-well region and electrically connected to the input/output terminal. A third isolation region is formed on the high voltage N-well region and having the drain of the PMOS transistor and the virtual N
+
region adjacent to both sides thereof. A fourth iso
J.C. Patents
United Microelectronics Corp.
Wojciechowicz Edward
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