Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
1999-11-29
2002-04-30
Eley, Timothy V. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S287000
Reexamination Certificate
active
06379223
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and apparatus for electrochemically-assisted or -augmented mechanical planarization, i.e., electrochemical-mechanical planarization (“EMP”), which method and apparatus enjoy particular utility in the manufacture of semiconductor integrated circuit devices.
BACKGROUND OF THE INVENTION
Chemical-mechanical polishing (CMP) techniques and apparatus therefor have been developed for providing smooth topographies, particularly on the surfaces of layers deposited on semiconductor substrates during integrated circuit manufacture. In such instances, rough topography results when metal conductor lines are formed over a substrate containing device circuitry, e.g., inter-level metallization patterns comprising a plurality of electrically conductive lines which may, inter alia, serve to interconnect discrete devices formed within the substrate. The metal conductor lines are insulated from each other and from vertically adjacent interconnection levels by thin layers of dielectric insulation material, and openings formed through the insulating layers provide electrical interconnection and access between successive such interconnection levels. In fabricating such type devices including multiple interconnection and insulative layers, it is desirable that the metallic and insulative layers have a smooth topography, inasmuch as it is very difficult to photolithographically image and pattern layers applied to rough surfaces. CMP can also be employed for removing different layers of material from the surface of a semiconductor substrate, as for example, following via hole formation in an insulating layer, when a metallization layer is deposited and then CMP is used to form planar metal via plugs embedded in the insulating layer.
Briefly, CMP processes utilized in semiconductor device manufacture involve mounting a thin flat workpiece, e.g., a semiconductor wafer substrate, on a carrier or polishing head, with the surface to be polished being exposed. The substrate surface is then urged against a wetted polishing surface, i.e., a rotating polishing pad, under controlled mechanical pressure, chemical, and temperature conditions. In addition, the carrier head may rotate to provide additional motion between the substrate and polishing pad surfaces. A polishing slurry containing a polishing agent, such as alumina (Al
2
O
3
) or silica (SiO
2
) finely-dimensioned particles is used as the abrasive material. Additionally, the polishing slurry contains a number of chemicals, including pH adjusting and stabilizing agents, as well as chemical oxidizing agents for chemically removing (i.e., etching) various components of the surface being planarized. The combination of mechanical and chemical removal of surface material during the polishing process results in superior planarization of the polished surface, vis-à-vis other planarization techniques.
Slurries used for CMP can be divided into three categories, depending upon their intended use: silicon (Si) polish slurries, oxide polish slurries, and metal polish slurries. Si polish slurries are designed to polish and planarize bare Si wafers and are typically composed of very small (i.e., about 20-200 nm diameter) abrasive particles, e.g., of silica (SiO
2
), alumina (Al
2
O
3
), or ceria (CeO
2
), suspended in a water-based liquid at a somewhat basic pH provided by a pH adjusting agent, typically a hydroxide-type base. Oxide polish slurries are designed to polish and planarize a dielectric layer on a wafer, typically a layer of silicon dioxide (SiO
2
), and are similarly composed of very small abrasive particles (i.e., about 20-1000 nm diameter) of, e.g., SiO
2
, Al
2
O
3
, or CeO
2
, suspended in a water-based liquid at a high (i.e., basic) pH.
Metals polish slurries are designed to polish and planarize conductive layers on semiconductor wafer substrates. The conductive layers are typically deposited on a dielectric layer and typically comprise metals such as tungsten (W), titanium (Ti), aluminum (Al), copper (Cu), alloys thereof, semiconductors such as doped silicon (Si), doped polysilicon, and refractory metal silicides. The dielectric layer typically contains openings (“vias”) that are filled with the conductive material to provide a path through the dielectric layer to previously deposited layers. After the conductive layer is polished, only the conductive material filling the vias remains in the dielectric layer.
Metal polish slurries utilized for such CMP of vias typically include very small particles (i.e., about 20-1000 nm diameter) of the above-mentioned abrasive materials, suspended in a water-based liquid. In contrast to the Si and oxide-type polishing slurries, the pH may be acidic (i.e., <5) or neutral and is obtained and controlled by addition of acid(s) or salt(s) thereof. In addition to the organic acid(s) or salt(s), metals polishing slurries include one or more oxidizing agents for assisting in metal dissolution and removal, typically selected from hydrogen peroxide, potassium ferricyanide, ferric nitrate, or combinations thereof.
However, the combination of acidic or neutral pH and presence of oxidizing agent(s), hereafter “oxidizer(s)”, in CMP metals polishing slurries can result in several disadvantages, drawbacks, and difficulties, including, inter alia:
(a) the oxidizer can continue to etch the electrically conductive material, e.g., metal, during “static” periods, i.e., periods when mechanical polishing is not being performed but the substrate surface remains in contact with the polishing slurry containing at least one oxidizer, e.g., upon completion of CMP but prior to removal of the substrate surface from contact with the slurry. As a consequence, unwanted static etching of the metallic features of the polished surface can occur, disadvantageously resulting in formation of depressions therein, referred to as “dishing”, which phenomenon remains a significant problem in metal CMP processes;
(b) the amount of oxidizer present in the metals polish slurries is not constant during the interval necessary for completion of the CMP processing, but rather varies during the course of CMP as a result of consumption thereof during the metal oxidation process. As a consequence, the concentration of oxidizer in the slurry, hence the rate of metal oxidation, is not controlled throughout processing, unless continuous, reliable detection/concentration measurement and replenishment means are provided, which means undesirably add to the cost of CMP processing;
(c) in some instances, the presence of oxidizer in the metals polishing slurry is particularly undesirable during a specific portion of the CMP processing. For example, the presence of oxidizer in the slurry during the later stage(s) of polishing frequently results in the above-mentioned problem of “dishing”, i.e., a height differential between a dielectric oxide layer and metallization features within an array of metallization features, as well as undesirable corrosion and “erosion”, i.e., a height differential between a dielectric oxide layer in an open field region and in an array of metallization features; and
(d) the presence of oxidizer(s) and spent oxidizer(s), e.g., peroxide, Fe ions, etc., in spent (i.e., waste) abrasive slurry adds to the complexity, problems, and expense associated with handling and disposal of the waste slurry in an environmentally acceptable manner.
U.S. Pat. No. 4,839,005 discloses a method and apparatus for providing mirror-smooth finishes to aluminum surfaces by applying a constant anodic potential to the surface via a passivation-type electrolyte solution, while simultaneously performing mechanical polishing thereof with an abrasive slurry or cloth. While such electrolytically-assisted polishing may dispense with the requirement for a chemical oxidizer in the polishing slurry or abrasive cloth, the application of a constant anodic potential renders the disclosed method/apparatus unsatisfactory for use in the planarization of workpieces comprising semiconductor wafers with surfaces having electricall
Redeker Fred C.
Sun Lizhong
Tsai Stan D.
Applied Materials Inc.
Eley Timothy V.
Moser Patterson & Sheridan
Nguyen Dung Van
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