Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-01-07
2002-09-03
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S783000, C438S786000
Reexamination Certificate
active
06444555
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the fabrication of semiconductor devices, and more particularly to establishing field effect transistor (FET) gate insulators.
BACKGROUND OF THE INVENTION
Semiconductor chips or wafers are used in many applications, including as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
It can readily be appreciated that it is important to electrically isolate various components of an integrated circuit from each other, to ensure proper circuit operation. As one example, in a transistor, a gate is formed on a semiconductor substrate, with the gate being insulated from the substrate by a very thin dielectric layer, referred to as the “gate oxide” or “gate insulator”. As the scale of semiconductor devices decreases, the thickness of the gate insulator layer likewise decreases.
As recognized herein, at very small scales, the gate insulator can be become so thin that otherwise relatively small encroachments into the gate insulator layer by sub-oxides from the substrate and from adjacent polysilicon connector electrodes can reduce the insulating ability of the gate insulator layer. This poses severe problems because under these circumstances, even very minor defects in the substrate can create electron leakage paths through the gate insulator, leading to catastrophic failure of the transistor.
To circumvent this problem, alternatives to traditional gate oxide materials, such as high-k dielectric materials including nitrides and oxynitrides that can be made very thin and still retain good insulating properties, have been proposed. Unfortunately, it is thought that these materials can degrade the performance of the transistor. Nitride, in particular, has been considered undesirable because it promotes unwanted leakage of electrons through the gate insulator layer.
Furthermore, as the gate insulator layer becomes very thin, e.g., on the order of nineteen Angstroms (19 Å), device integration becomes highly complicated. Specifically, it is necessary to etch portions of the polysilicon electrodes down to the substrate, but stopping the etch on a very thin, e.g., 19 Å gate insulator layer without pitting the substrate underneath becomes problematic. Accordingly, the present invention recognizes that it is desirable to provide a gate insulator layer that can be made very thin as appropriate for very small-scale transistors while retaining sufficient electrical insulation properties to adequately function as a gate insulator, and while retaining sufficient physical thickness to facilitate device integration, without degrading performance vis-a-vis oxide insulators.
BRIEF SUMMARY OF THE INVENTION
A method for making a semiconductor device includes providing a semiconductor substrate, and establishing an oxide base film on the substrate. The substrate is annealed, preferably in ammonia at temperatures up to eleven hundred degrees Celsius (1100° C.), after which FET gates are formed on portions of the film. The preferred base film defines a thickness of no more than twenty four Angstroms (24 Å). However, after annealing, the base film has been converted to a nitrided oxide film having electrically insulating properties which correspond to that of a thinner conventional oxide film having a physical thickness of only 20 Å thick to inhibit undesired tunneling through the nitrided oxide film, thereby resulting in a relatively lower standby current for a relatively higher drive current and capacitance.
Other features of the present invention are disclosed or apparent in the section entitled
DETAILED DESCRIPTION OF THE INVENTION
REFERENCES:
patent: 4490900 (1985-01-01), Chiu
patent: 5017979 (1991-05-01), Fujii et al.
patent: 5219773 (1993-06-01), Dunn
patent: 5254489 (1993-10-01), Nakata
patent: 5656516 (1997-08-01), Suzuki
patent: 5891809 (1999-04-01), Chau et al.
patent: 5908313 (1999-06-01), Chau et al.
patent: 6048769 (2000-04-01), Chau
patent: 6107174 (2000-08-01), Hori
patent: 6124171 (2000-09-01), Arghavani et al.
patent: 6133093 (2000-10-01), Prinz et al.
patent: 0847079 (1998-10-01), None
The article by Gupta et al. entitled, “Hot-carrier-induced degradation in nitrided oxide MOSFET's” in IEEE Transactions on Electron Devices, vol. 36(3), Mar. 3, 1989, pp. 577-588.*
Effect of Nittrogen Distribution in Nitrided Oxide prepared by Rapid Thermal Annealing on its Electrical Characteristics/Yasushi Naito, Takashi Hori, Hiroshi Iwasaki, and Hideya Esaki, pp. 633-637.
Advanced Micro Devices , Inc.
Chaudhuri Olik
Kielin Erik
LaRiviere Grubman & Payne, LLP
LandOfFree
Method for establishing ultra-thin gate insulator using... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for establishing ultra-thin gate insulator using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for establishing ultra-thin gate insulator using... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2862764