Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-06-28
2002-01-15
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S238000, C438S610000, C438S615000, C257S200000, C257S270000
Reexamination Certificate
active
06339024
ABSTRACT:
FIELD OF THE INVENTION
This application relates to the manufacture of integrated circuits.
BACKGROUND OF THE INVENTION
A major problem with integrated circuits (ICs) is that they are sensitive to pressure. This is a problem during manufacture of the integrated circuit (IC) because, just prior to encasing the circuit in plastic, the circuit is tested by having a set of probes pushed against critical conductive points on the top layer and measurements taken. Ironically, the very act of applying pressure through the testing probes causes damage to a percentage of the tested ICs, necessitating their rejection. The dielectrics used in semiconductors are generally structurally weak and are particularly sensitive to pressure. The problem is aggravated by the need for ever frailer dielectrics as the need for increased speed increases. Thick and strong dielectrics slow electric signals.
Another drawback with prior art ICs is the need to apply a top layer of aluminum that shorts out all of the conductive points, and then etch the layer so as to electrically connect the conductive points together correctly. This metallic (i.e., not solid-state) topmost layer, commonly referred to as the TD layer, also serves to connect the appropriate conductive points to the metal connectors, or contacts, that lead outside the plastic casing and plug into a matching IC socket.
BRIEF SUMMARY OF THE INVENTION
Disclosed is a method of manufacturing integrated circuits by introducing a thicker final solid state level with a thicker conductive structure in the final solid state level of chip manufacturing. The conductive structure in this layer, also known as the TV layer, will be at least 1.5 &mgr;m thick, thereby creating raised conductive points that have sufficient structural strength to resist the pressures of testing probes and thereby protect the lower layers from damage during IC testing.
In a preferred embodiment of the invention, the typical etched aluminum TD layer of the prior art is discarded in favor of gold deposited upon the raised copper conductive points. The gold is actually cheaper than aluminum because it can be deposited directly where desired, thereby eliminating a costly etching operation. The gold is easily spot welded for wire bonding to the IC contacts.
REFERENCES:
patent: 4368573 (1983-01-01), DeBrebisson et al.
patent: 5171711 (1992-12-01), Tobimatsu
patent: 5975420 (1999-11-01), Gogami et al.
patent: 6076737 (2000-06-01), Gogami et al.
patent: 6207570 (2001-03-01), Mucha
Heidenreich, III John E.
Petrarca Kevin S.
Rubino Judith M.
Sambucetti Carlos J.
Volant Richard P.
Cantor & Colburn LLP
Elms Richard
Luu Pho M.
Petraske Eric W.
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