Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-01-11
2002-04-02
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06367056
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to timing analyses for determining whether timing requirements are met in electronic designs. More specifically, the invention relates to rapid techniques for performing such timing analyses by recalculating a timing parameter for only a portion of the electronic design.
Electronic design automation (“EDA”) is becoming increasingly complicated and time consuming, due in part to the greatly increasing size and complexity of the electronic devices designed by EDA tools. Such devices include general purpose microprocessors as well as custom logic devices including Application Specific Integrated Circuits (“ASICs”). Examples of ASICs include non-programmable gate arrays, Field Programmable Gate Arrays (“FPGAs”), and Complex Programmable Logic Devices (“PLDs” or “CPLDs”). The design of even the simplest of these devices typically involves generation of a high level design, logic simulation, generation of a network, timing simulation, etc.
Timing analyses or simulations are performed to determine whether a particular design meets timing requirements specified by the designer. Such requirements may be necessary to ensure compliance with the requirements of an application for which the device will be used. Usually, timing simulation cannot be performed until the design has been compiled to the point where various gate level entities (representing at least a subsection of the overall design) are synthesized and placed and the lines therebetween are routed on a target hardware device. This compilation requires that an initial design (or a significant piece of it) be functionally completed.
Quite typically, a designer (or the compiler itself) will modify a design, after an initial compilation. This may be required when a timing simulation or other design analysis conducted after (or as part of) compilation indicates a problem. Or, the product requirements may change in the middle of the device's development. Regardless of why a design change is necessary, that change requires a recompile. With some or all such recompiles, the designer conducts timing analyses.
In a hierarchical or “top down” design process, initial designs may specify generic logic blocks (e.g., an arithmetic logic unit) without specifying the gate level logic. Other parts of the design may be completed to the gate level. Such initial designs are very coarse; i.e., they are far removed from the final exact hardware layout of the whole device. Results of timing simulations performed after compilation at these early stage designs will necessarily lack precision. The design parameters are not completely defined at the silicon level and the design will likely change/evolve as development progresses. Nevertheless, a timing analysis can be performed on these initial designs in order to determine whether the timing parameters are within the general range (“ballpark”) specified by the designer. In later stage designs, the timing parameters can be gauged with more precision and accuracy.
If a design is being driven primarily by timing considerations so that the goal is a very fast device, obviously the timing simulations must be performed very frequently during the design process. In this case, a designer may conduct timing simulations with each small design modification. If the design is driven primarily by some other parameter such as logic density, then timing simulations may not be necessary quite as often. But regardless of whether the design is driven more by timing constraints or area constraints, some form of timing analysis must be frequently performed during the design process.
To guide later stages of design and to verify that timing requirements are met, timing analyses are typically performed before, during, and after “fitting.” Fitting is a process whereby a compiler fits an electronic design onto a target hardware device. For PLD designs, fitting can be divided into three phases: partitioning, placement, and routing. Partitioning involves grouping logic cells which share common inputs/outputs and/or feed one another. This grouping is intended to minimize the amount of long distance routing. Cells that frequently communicate with each other or share common resources should be placed close together so that most routing is local. During the placement phase, the various logic groups or blocks created during partitioning are assigned to specific geographic locations on a hardware device. Finally, routing makes interconnections between the various logic blocks that are now placed on the hardware device. Normally, the timing of each new “fit” of a design is checked.
While the primary goal of timing analyses is to ensure that the resulting electronic design and constituent circuits are meet timing requirements (i.e., they are fast), it is also important to ensure that the timing analyses themselves can be executed rapidly. Each compilation and associated timing simulation consumes significant time, so multiple recompiles/timing simulations translates to significantly longer development times. This can greatly slow the time to market for an integrated circuit under design. Because PLDs rely on a short time to market as a major selling point, slow development can erase any commercial advantage.
The problem is compounded because maximum CPLD device sizes are increasing at a speed slightly greater than that predicted by Moore's law (i.e., each new chip contains roughly twice as much capacity as its predecessor, and each chip is released within 18-24 months of the previous chip). If compilation time was a linear function of design size then it would be expected that the time to compile the largest device on the most powerful computer would remain approximately constant. Unfortunately, compile times are typically proportional to n
2
, where n is the number of logic elements on a device. This means that a design twice as big takes four times as long to compile (on a given computer). Consequently, the compile times for the largest devices are accelerating. It is not uncommon for large projects to compile for about 24 hours or more on a modern workstation. Obviously, the fastest compilers (and associated timing simulators) will become critical components of integrated circuit design environments.
It appears that most available design products do not perform timing analysis as rapidly as they might. Therefore, there is a need for more rapid techniques for performing timing analyses in large and/or complex electronic designs.
SUMMARY OF THE INVENTION
The present invention provides an “incremental” timing analysis or simulation in which much of the results of a previous timing simulation are used. The previous timing results were obtained for a previous electronic design which was slightly modified by the designer. The portion of the design affected by the modification is identified and its timing is recalculated. The timing for the remainder of the design is left as is from the previous design. This speeds the timing analysis for the modified design because less than the entire design need be considered in the new timing analysis.
In this invention, the timing analyses of interest are performed after considering at least one and usually two “regions” associated with a design change: (1) the region of the design change itself and (2) a possibly larger region having its timing influenced by the design change.
The process of interest is triggered when a “first electronic design” is converted to a “second electronic design.” This involves taking the first design and modifying a portion of it by refitting that area, changing the logic in that area, or otherwise changing that area. In an important embodiment, it involves refitting the portion. As a result of the modification, some portion of the first design will be modified. That portion is referred to herein as a “modified portion.” The remainder of the design is referred to as the “unmodified portion.” Thus, the second electronic design includes a modified portion and an unmodified portion. The modified portion may have had t
Altera Corporation
Beyer Weaver & Thomas LLP
Lee Calvin
Smith Matthew
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