Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-01-19
2002-03-19
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S264000, C438S301000, C438S304000, C438S596000
Reexamination Certificate
active
06358827
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming polysilicon gate field effect transistors.
(2) Background to the Invention and Description of Related Art
Computer memory consist of vast arrays of storage cells which can be addressed by wordlines and bitlines. The most commonly used DRAM (dynamic random access memory) cell design comprises a transfer gate (usually an MOS field-effect-transistor (MOSFET) and a storage node consisting of a capacitor plate connected to the MOSFET drain. Memory cells for ROMs (read only memories), PROMS (programmable ROMs) and EEPROMs (electrically erasable PROMS) are similarly arranged in rectangular arrays and are addressed by wordlines and bitlines but typically have their storage nodes formed by a floating gate which lies subjacent to an addressable control gate. Memory cells require a high cell density in order to achieve high performance and cost efficiency.
The simplicity of cell design permits the interconnection of elements of the transfer MOSFET, thereby permitting simpler and more effective array design. Conventionally, the control gates of all the MOSFETs in a wordline are formed of a single polysilicon band, traversing alternately over field oxide and cell gate regions. Likewise, the sources of the MOSFETs in a DRAM bitline string may be formed of a single diffusion or individual source diffusions, isolated by field oxide, may be interconnected by a superjacent addressable bitline. The interconnection of source elements by a diffusion band is found in EEPROM memory arrays. The drains of each of the MOSFETs must however remain unique and therefore electrically isolated.
A flash memory cell is descended from an EEPROM, having a floating gate which is charged and discharged, by trapping and releasing channel hot electrons emitted from the source through an ultra thin tunnel dielectric. A sufficient hot electron flow is achieved by biasing the control gate to produce a high source/drain current. Traditionally, floating gates and control have been formed by photolithographically patterning a deposited polysilicon layer. The minimum achievable planar dimensions are thereby limited by the photolithographic resolution of the technology. Keschtbod, U.S. Pat. No. 5,479,368 shows a method of avoiding the photolithographic resolution limit by forming a floating gate using sidewall technology. The minimum planar width of the floating is thereby essentially determined by the thickness of the conformal polysilicon layer from which the floating gate is formed. Ogura, U.S. Pat. No. 6,074,914 shows another process for forming a floating gate of split gate flash transistor from a polysilicon sidewall.
While the floating gate is completely isolated from other cell components, there is no need to make further connection to it. The floating gate is also small, each unit being confined to a single cell. Unlike the control gate which is part of a relatively long wordline, the floating gate conductivity need not be reinforced by silicidation as does the control gate.
Morihara, U.S. Pat. No. 5,404,038 shows a control gate of a memory cell with a circular design formed from a polysilicon sidewall. The polysilicon sidewall control gate is formed in the corner of a step formed by an opening in an epitaxial layer. The oxide gate dielectric extends beneath both the bottom and side of the polysilicon sidewall. The polysilicon which extends over the field isolation is masked by photoresist during sidewall etching to form a broader wordline which is attached a narrower gate element over the active region which has a curved profile. Because this is a corner structure without self-aligned LDD regions, and is connected to broader polysilicon wordlines which can be contacted in the conventional manner, there is no need to have a rectangular cross section of the section which traverses over the channel.
He, et. al. U.S. Pat. No. 6,063,668 shows a process for sealing recesses with polysilicon spacers in order to prevent the formation of ONO fences and polysilicon stringers, cause by mis-alignment of a polysilicon etch. Wu, U.S. Pat. No. 6,010,934 shows a method using free standing polysilicon spacers as a mask for making a silicon oxide hardmask which in turn is used to etch tiny silicon islands for single electron transistors. The polysilicon spacers are used as formed, having a curved taper on the side opposite to the step on which they were formed.
A major source of problems in using a sidewall structure as a conductive element in an integrated circuit, is the natural taper of the sidewall. Unlike patterned elements which have planar upper surfaces which can be easily treated and contacted in further processing steps, the natural sidewall taper is not compatible with such procedures. While a masking procedure to provide a broader conductive stripe over field isolation could satisfactorily address interconnection problems, the formation of insulative sidewalls to protect implanted LDD regions from a source/drain implant would be compromised by a non-rectangular sidewall gate structure. For example, in a self-aligned polysilicon gate MOSFET formed by a salicide process would present gate-to-source/drain bridging problems if the gate were formed by the conventional sidewall etching process. In addition, insulative sidewall formed along the edges of a polysilicon gate formed the conventional sidewall process would not be symmetrical. This will be shown in the following illustration:
Referring to
FIGS. 1A through 1E
, there are shown the processing steps that would be used to form a polysilicon control gate over a gate oxide by a sidewall process using the conventional methods taught to form a polysilicon floating gate. In
FIG. 1A
, an oxide layer
12
is patterned over a silicon wafer
10
by anisotropic etching to form a step
13
. A thin gate oxide
14
is then grown on the exposed silicon. Next a conformal polysilicon layer
16
is deposited, typically by a CVD (chemical vapor deposition) method. Referring next to
FIG. 1B
, the polysilicon layer
16
is anisotropically etched back to the oxide leaving a sidewall portion
17
next to the step
13
.
The width “w” of the polysilicon sidewall at it's base where it contacts the gate oxide is a critical dimension of the control gate, determined by the device design. Consequently The initial thickness of the polysilicon layer is chosen achieve this width. In order to form LDD (lightly doped drain) regions by the conventional self-aligned MOSFET process, the oxide layer
12
and the exposed portion of the gate oxide
14
are removed by wet etching or by plasma etching, leaving a free standing polysilicon sidewall gate electrode
17
. This is illustrated in FIG.
1
C. LDD regions
18
are then formed by implanting impurities, for example arsenic, if the wafer
10
is p-type.
At this stage of processing the cross section of the MOSFET appears normal and conventional except for the curved taper on one side of the polysilicon gate electrode
17
. If conventional processing, that is forming oxide sidewalls, implanting a source/drain, and silicidation, were to continue, serious problems would occur. Referring to
FIG. 1D
a conformal oxide has been deposited and anisotropically etched back in the manner of a conventional gate sidewall process. Unlike the conventional result, however, if anisotropic etching is halted when the silicon substrate is reached, essentially no top portion of the polysilicon gate is exposed. It would therefore require an over-etch in order to drive the oxide sidewalls
19
further down along the sides of the polysilicon gate
17
. The resulting cross section is shown in FIG.
1
E. An additional problem is that the oxide sidewalls
19
are unsymmetrical and would result in unequal LDD lengths on each side of the gate.
If the oxide sidewalls are further driven down by over etching in order to exposed a portion of the polysilicon at the top, as shown in
FIG. 1E
, the length
Chen Han-Ping
Hsu Cheng-Yuan
Sung Hung-Chen
Ackerman Stephen B.
Lindsay Jr. Walter L.
Niebling John F.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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