Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-02-18
2002-04-16
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S353000, C257S390000, C257S523000
Reexamination Certificate
active
06373099
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device for use in an electronic circuit for a variety of technical fields such as an automobile, an electric power generating plant, an artificial satellite as well as an OA machine and an electronic product for a private use such as a copying machine, a facsimile machine, a printer and a video camera, and a method of manufacturing the semiconductor device.
In particular, the present invention relates to a semiconductor memory device for storing a required information signal.
2. Related Background Art
FIGS. 45A and 45B
illustrate the structure of a semiconductor memory capable of storing and programming data only one time, the semiconductor memory being constituted by an MOS type field effect transistor (hereinafter called an “MOSFET”) serving as an insulated gate type field effect transistor and a memory cell having an insulating film.
A memory of the aforesaid type has been disclosed in, for example, “A New Programmable Cell Utilizing Insulator Breakdown”, IDEM′ 85, pp 639 to 642.
Another type semiconductor arranged as shown in
FIG. 46
has been known.
FIG. 46
is a cross-sectional view which illustrates the semiconductor memory of the aforesaid type. Referring to
FIG. 46
, reference numeral
120
represents an n-type substrate,
121
represents a p
+
drain,
122
represents a P
+
source,
123
represents a floating gate,
124
represents an insulating layer,
125
represents a drain wiring and
126
represents a source wiring. The floating gate
123
is manufactured by, for example, embedding a polycrystalline silicone in a silicon oxide film.
A transistor for use in ULSIs and having a gate length of sub-micron order has been developed thanks to progress of the fine processing technology.
FIG. 101
is a schematic cross sectional view which illustrates an LDD (Lightly Doped Drain) structure as a typical MOS type field effect transistor (hereinafter called a “MOSFET”).
Referring to
FIG. 101
, reference numeral
201
represents a P type semiconductor substrate,
202
represents a field oxide film,
203
and
204
respectively represent n
+
layer of the source region and that of the drain region and
205
represents a gate insulating film,
206
represents a gate electrode. Reference numerals
207
and
208
respectively represent n
−
layer provided for the purpose of relieving the field concentration taken place adjacent to the gate of the source region and that of the drain region,
209
represents a channel dope layer formed by an ion injection operation for the purpose of making the threshold to be a desired value and
210
represents a P
+
layer.
However, the transistor structured as described above arises the following problems.
A first problem takes place in that drain current I
D
and the mutual inductance (gam) are too small due to the presence of the n
−
layers
207
and
208
. A second problem arises in that the mobility is deteriorated, and a third problem will arise in that the gate width W cannot be fined with the similar scaling to that for use to fining the gate length L.
The aforesaid problems will now be described.
FIG. 102
is a graph which illustrates an example of the relationship between the length of the channel and the drain current as disclosed in K. Yano, M. Aoki, and T. Masahara Extended Abstracts of the 18th (1986 International) Conference on Solid State Devices and Material (1986) PP85 to 88.
FIG. 102
shows results of comparisons made between a drain voltage V
D
of 0.1 V, 5 V, temperature of 77 K. and 300 K.
As can be understood from
FIG. 102
, parasitic drain resistance generated due to the n
−
layers
207
and
208
causes the decrease of the length of the channel and the increase in the drain current are not in proportion to each other as designated by a dashed line XA but are made as designated by a solid line XB. Referring to
FIG. 102
, symbol XC shows measured values. Since a large drain current is not obtained as described above, the mutual conductance characteristics (the gm characteristics) are deteriorated.
A rule of scaling a typical MOSFET is shown in Table 1.
TABLE 1
Parameter
Scaling Ratio
Length of channel
l/K
Width of channel
l/K
Thickness of gate oxide film
l/K
Depth of joint
l/K
Thickness of Depletion layer
l/K
Concentration of impurities
K
in channel
Voltage
l/K
As can be understood from Table 1, the punch-through current between the source and the drain generated due to fining of the channel length L can be prevented by raising the impurity concentration Na of the region which is formed into the channel. However, the concentration of the impurities in the channel is raised, the mobility of the carrier is lowered and thereby the gm characteristics are deteriorated. It might therefore be considered feasible to employ a method in which the p
+
layer
210
is brought near the gate insulating film
205
. In this case, the field intensity in the vertical direction in relation to the direction in which the carrier is moved is raised. Therefore, also the mobility of the carrier is lowered while maintaining the correlative relationship as shown in
FIG. 103
(which illustrates the relationship between the field intensity (axis of abscissa) in the vertical direction and the mobility (axis of ordinate) as disclosed in, for example, A. G. Sabnis et al. IEDM 79 PP18 to 21, where XD, XE and XF are measured values when the power supply voltage was 0.1 V, −5.0 V and −20.0 V, respectively).
That is, the characteristics of the MOSFET having the gate length L ranged from 0.5 to 0.8 &mgr;m can be improved to a certain degree according to the scaling rule shown in Table 1. However, the gate length L is smaller than the aforesaid range, the drain current and the gm characteristics excessively deteriorated. Furthermore, the fining operation will cause the proportion of the wiring section to be enlarged. Therefore, there is a desire of a transistor having further improved gm characteristics. However, it can be met by only widening the gate width W under the present conditions. Therefore, the original object of fining the size cannot be achieved.
Also a GOLD type (Gate Overlap Lightly Doped Drain) MOSFET which is a modification to the LDD type MOSFET encounters the aforesaid problems.
In order to overcome the aforesaid problems experienced with the MOSFET structured as described above, a surrounding gate transistor (SGT) has been disclosed which is arranged in such a manner that four gate electrodes face one another as suggested in H. Tadato, K. Sunoushim, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, and F. Masuoka IEDM (International Electron Device Meeting) (1988) PP222 to 225. The structure of it is shown in
FIGS. 66 and 67
.
FIG. 66
is a perspective view and
67
is a cross section taken along line A-A′.
Referring to
FIGS. 66 and 67
, reference numeral
215
represents a substrate,
216
represents a p well layer,
217
represents a source region,
218
represents a gate electrode,
219
represents a gate insulating film,
220
represents a drain region and
221
represents a drain outlet electrode. In the aforesaid structure, the gate electrode
218
is formed to surround the channel region. Therefore, the following advantages can be obtained: the concentration of the electric field can be relieved, the adverse effect of the hot carrier or the like can be eliminated and the control of the potential of the channel portion by using the gate can be easily performed.
FIG.
104
A and
FIG. 104B
respectively are a plan view and a circuit diagram which illustrates a CMOS invertor circuit which utilizes an SGT.
FIGS. 105 and 106
are cross-sectional views respectively taken along line A-A′ and C-C′ of FIG.
104
A. The contact portions between Vin and PMOSFET and NMOSFET are represented by
230
and
231
.
In the aforesaid conventional transistor, the portion between the source and the drain is not conductive in a normal state. Writing can be performed b
Ichikawa Takeshi
Ikeda Osamu
Inoue Shunsuke
Kikuchi Shin
Nakamura Yoshio
Chaudhuri Olik
Peralta Ginette
LandOfFree
Method of manufacturing a surrounding gate type MOFSET does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a surrounding gate type MOFSET, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a surrounding gate type MOFSET will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2858942