Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2001-03-13

2002-09-24

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S369000, C257S501000, C438S128000, C438S129000, C438S199000

Reexamination Certificate

active

06455901

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-093934, filed Mar. 30, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more specifically, to a semiconductor integrated circuit operated under a plurality of power supply sources and comprising a complementary MIS logic circuit operated at low power supply voltage.
Recently, the number of semiconductor elements formed on a chip has significantly increased. Several hundreds of millions of semiconductor elements are integrated per chip in a gigabit-order semiconductor memory, and several tens of thousands to tens of millions of semiconductor elements are integrated per chip in a 64-bit microprocessor. The number of semiconductor elements formed on a chip can be improved by reducing the size of semiconductor elements. An MOS transistor having a gate length of 0.15 micrometers is now used in a 1 G-bit DRAM (Dynamic Random Access Memory). An MOS transistor having a gate length of 0.1 micrometer or less will be employed in the future as the number of semiconductor elements formed on a chip is further increased.
However, the miniaturized MOS transistors are degraded due to hot carriers and a dielectric film breakdown due to TDDB (time dependent dielectric breakdown). In addition, as a channel length of an FET decreases, a threshold voltage of the FET also decreases. To prevent the threshold voltage from decreasing, an impurity concentration of a substrate region or a channel region of the FET is increased. However, as the impurity concentration increases, a source/drain junction voltage of the FET also decreases.
Reducing a power supply voltage is effective in maintaining the reliability of miniaturized MOS transistors and FETS. More specifically, by reducing the power supply voltage, the electric field in a lateral direction between the source and drain is weakened preventing the generation of hot carriers. Furthermore, by reducing the power supply voltage, the electric field in a longitudinal direction between the gate and bulk is weakened preventing TDDB. Furthermore, a reverse bias voltage applied to the junction between the drain and bulk is decreased by reducing the power supply voltage. In this way, it is possible to cope with a decrease in a breakdown voltage of the junction.
Recently, the market for portable information devices has remarkably increased. Most of the portable information devices employ a lightweight power supply, such as a lithium ion battery having a high energy density. However, the three volts (3V) of the lithium ion battery is higher than the breakdown voltage of a miniaturized MOS transistor. Therefore, when the lithium ion battery is applied to a circuit comprising a miniaturized transistor, a power supply voltage converter must be used to reduce the voltage. The power consumed during the operation of a CMOS circuit used in a logic circuit is not only proportional to an operational frequency, but also proportional to the square of the power supply voltage. Therefore, reducing the power supply voltage significantly lowers the power consumption in the chip.
Using a portable device for a long time requires using a battery with a high energy density, having a highly efficient power supply voltage converter, and operating an integrated circuit at a low voltage. Power consumption can be saved further if a reduced power supply voltage can be used in a power-consuming microprocessor and base band LSI.
The portable information device also requires a memory device such as a DRAM or an SRAM in addition to logic circuits. However, unlike with logic circuits, attempts to reduce power consumption in memory devices have not been aggressively made. To reduce soft errors in a DRAM, a sufficient amount of electric charge must be kept in a cell in the DRAM. Furthermore, low speed operation at a low power supply voltage in the SRAM must be avoided.
Therefore, at present, only elements capable of operation at a power supply voltage of about 1.5V are put to practical use. However, since a logic circuit can operate at a voltage far smaller than the power supply voltage for a memory device, a multi-power source capable of supplying various power supply voltages is used in an LSI comprising memory circuits and logic circuits.
FIG. 1
shows a semiconductor integrated circuit
604
, for use in portable information devices, in which an on-chip memory circuit
603
and a logic circuit
602
are integrated in the same chip. Its power supply system is also shown in FIG.
1
.
The power supply system includes a lithium ion secondary battery
600
and a power supply voltage converter
601
. The output voltage, 3V, of the lithium battery
600
is converted to 0.5V by the power supply voltage converter
601
. The converted voltage is supplied to the logic circuit
602
. Since the on-chip memory circuit
603
generally requires a power supply voltage of 1.5V to 2.0V or more for operation, a power supply voltage of 3V is supplied to the memory circuit
603
from the lithium battery
600
.
In the circuit arrangement of
FIG. 1
, if the power supply voltage to the logic circuit can be reduced from 3V to about 0.5V, the power consumption during the operation time can be drastically reduced by 95%, in theory. However, if the power supply voltage for a general CMOS circuit operating at 3V to 2V is just simply reduced, the operation speed of the CMOS circuit is lowered or the operation stops.
To overcome these problems, a threshold voltage of a MOS transistor must be reduced along with a decrease in a power supply voltage. To construct a logic circuit that operates at a low power supply voltage of 0.5V, for example, a MOSFET having a threshold voltage of about 0.1 to 0.15V, which is about ⅓ of the threshold voltage of a conventional MOSFET, should be used.
However, with such a low threshold voltage, the leakage current during an off-time of a MOSFET drastically increases by a factor of 100 if an S factor, which determines a sub-threshold characteristic of a MOSFET, is 100 mA/decade, for example. Therefore, although the power consumption during an operation time is reduced simply by reducing the power supply voltage, the power consumption during a stand-by time is significantly increased. This means that the usable time of a device is shortened due to the stand-by time power consumption. Therefore, the reduced power supply voltage application as mentioned above is not suitable for semiconductor integrated circuits used in portable information devices.
FIG. 2
shows an improved circuit to overcome the aforementioned problems. In the circuit, an extremely low voltage of 0.5V is supplied to a semiconductor integrated circuit
705
by a power supply voltage converter
701
and a power supply voltage VD
1
(0.5V) is supplied to a logic circuit
702
. This attains low power consumption during an operation time.
Furthermore, a positive voltage generator
703
and a negative power voltage generator
704
are provided to generate a voltage that is greater than a power supply voltage VD
1
and a voltage that is less than a ground potential VSS, respectively.
The supply voltages generated by the voltage generators
703
and
704
are applied to an n-well and a p-well of the logic circuit
702
, respectively, to reduce an absolute value of a threshold voltage of the MOSFETs in the logic circuit
702
during a normal operation time to increase the operation speed. In addition, the absolute value of the threshold voltage of the MOSFETs within the logic circuit
702
is increased during the stand-by time to reduce the leakage current during the OFF-time to lower the power consumption.
However, when supplying an extremely low power supply voltage of 0.5V, problems usually occur. For example, a charge pump system is usually used for the positive voltage generator
703
and the negative voltage generator
704
in the semiconducto

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