Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-08-29
2002-09-17
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185220, C365S189070
Reexamination Certificate
active
06452839
ABSTRACT:
TECHNICAL FIELD
This invention relates to integrated circuit memory devices, and, more particularly, to a method and apparatus for providing high density, high storage capacity, low power, nonvolatile memory devices.
BACKGROUND OF THE INVENTION
Single electron devices, and particularly single electron memory cells, are presently of great interest, due to potential advantages in memory cell size and power dissipation, compared to memory technologies currently in use. As used herein, the term “single electron device” refers to an electronic device capable of providing a repeatable and measurable response to the presence or absence of a single electron.
As device sizes have shrunk over the last several decades, the number of electrons contributing to the drain current in field effect transistors (“FETs”) used in memory devices has correspondingly decreased. Extrapolation from these trends suggests that in another decade, FETs will have drain currents including as few as ten electrons at a time. When so few electrons contribute to a current and therefore to a signal, normal fluctuations in the number of electrons present in a volume of semiconductor material can lead to uncertainty or error in the signal that the current represents.
Memories using single electron memory cells provide certainty in numbers of electrons representing data in a memory cell and therefore help to avoid problems due to fluctuations in the number of electrons that are present in a transistor at one time. Memory cells employing single electron transistors are also extremely simple and can be quite small. For example, a memory structure employing vertically stacked cells to provide an area per bit of 0.145 squared is described in “A 3-D Single-Electron-Memory Cell Structure with 2F
2
per bit” by T. Ishii et al. (IEDM 97), pp. 924-926.
The combination of size, power requirements and simplicity make single electron structures promising candidates for very high capacity memory integrated circuits. This is discussed in more detail in “Single-Electron-Memory Integrated Circuit for Giga-to-Tera Bit Storage” by K. Yano et al., 1996 Intl. Solid State Circuits Conf. (Feb. 9, 1996), pp. 266-267 and “A 128 Mb Early Prototype for Gigascale Single-Electron Memories” by K. Yano et al., 1998 Intl. Solid State Circuits Conf. (Feb. 7, 1998), pp. 344-345.
FIG. 1A
is a simplified schematic diagram of a typical two-terminal single electron device
20
, in accordance with the prior art. The single electron device
20
includes first
22
and second
24
electrodes and an island
26
formed from conductive material, which may be semiconductor material, as discussed in U.S. Pat. No. 5,731,598, entitled “Single Electron Tunnel Device And Method For Fabricating The Same” issued to H. Kado et al. (Mar. 24, 1998). The first
22
and second
24
electrodes are each separated from the island
26
by small insulating gaps
28
,
28
′. The first
22
and second
24
electrodes, the island
26
and the gaps
28
,
28
′ are all collectively mounted on an insulating substrate
30
or are surrounded by an insulator. The gaps
28
,
28
′ may be formed of any insulating material but must be small enough to allow conduction band electrons
32
(hereinafter “electrons”) to tunnel through them in response to a voltage V coupled across the first
22
and second
24
electrodes. The voltage V is provided by an external source, represented in
FIG. 1A
by a battery
34
.
A first condition for trapping one or more electrons
32
on the island
26
is that the resistance R between the island
26
and other structures on the substrate
30
must be greater than a quantum resistance R
k
, as is discussed, for example, in “Single-electron devices” by H. Ahmed et al., Microelectronic Engineering
32
(1996), pp. 297-315, and “Single electron electronics: Challenge for nanofabrication” by H. Ahmed, J. Vac. Sci. Technol. B 15(6) (November/December 1997), pp. 2101-2108. When the first
22
and second
24
electrodes and the island
26
are mounted on the insulating substrate
30
and are surrounded by an insulator such as air, a primary resistance R between the island
26
and any other structure is set by tunneling resistances R
t
associated with the gaps
28
,
28
′ separating the island
26
from the first
22
and second
24
electrodes. The quantum resistance R
k
equals h/q
2
, or about 26 k&OHgr;, where h is Planck's constant and q represents the charge of a single electron. This first condition will be satisfied for all of the examples considered herein but is included for completeness sake.
A second condition is that allowed states for these electrons
32
must be separated from a conduction band edge E
C
by an “electron charging energy” that is given as q
2
/2C, where C represents a capacitance of the island
26
. In other words, a first electron
32
that is introduced onto the island
26
will occupy an allowed state having a potential energy that is greater than that of the conduction band edge E
C
for the material forming the island
26
by q
2
/2C.
A third condition is that, for the electron or electrons
32
to be trapped on the island
26
, the electron charging energy q
2
/2C must be substantially greater than an average thermal energy kT, or q
2
/2C>kT, where k represents Boltzmann's constant and T represents temperature in Kelvin. The capacitance C must be on the order of one attoFarad for electrons
32
to be trapped on the island
26
for any appreciable length of time at room temperature (kT=0.026 eV at room temperature). For example, an island
26
having a capacitance of 10
−16
F is about 100 nanometers in diameter but can only exhibit single-electron effects at temperatures at or below about 4 Kelvin. Islands
26
having diameters of one to five nanometers exhibit significant single-electron effects at room temperature (circa 300 K).
FIG. 1B
is a simplified potential energy diagram for the device
20
of
FIG. 1A
showing a potential well
40
, in accordance with the prior art.
FIG. 1B
shows Fermi levels (“E
F
”)
42
,
44
in the first
22
and second
24
electrodes, respectively, a lowest allowed state
46
for one electron
32
in the potential well
40
on the island
26
, and energy barriers
48
,
48
′ associated with insulating materials forming the gaps
28
,
28
′, respectively. An important property of the device
20
of
FIG. 1A
is that no significant current can flow through the device
20
until a magnitude of the potential V due to the external source
34
equals or exceeds the electron charging energy or V≧q
2
/2C.
FIG. 1C
is a simplified potential energy diagram illustrating the potential V setting the Fermi level
42
at the left side of the Figure equal to the lowest allowed state of the potential well
40
, i.e., at the onset of conduction, in accordance with the prior art.
FIG. 1D
is a simplified graph of an I-V characteristic
50
for the device
20
of
FIG. 1A
, in accordance with the prior art. The I-V characteristic
50
shows essentially no conduction until the applied voltage V reaches a threshold V
C
, causing the Fermi level
42
on the electron supply side to be equal to the electron charging energy q
2
/2C. The region of essentially no conduction is known as the Coulomb blockade region. When the applied voltage V reaches the threshold V
C
, known as the Coulomb gap voltage, the energy barrier effectively vanishes. Linear I-V dependence is seen in
FIG. 1D
for voltages having an absolute magnitude exceeding V
C
.
FIG. 2
is a simplified schematic illustration of a typical field effect transistor (“FET”)
60
that includes the island
26
of
FIG. 1A
for storing one or more electrons
32
, in accordance with the prior art. The FET
60
includes all of the elements of the two-terminal device
20
of FIG.
1
and additionally includes a gate
62
having a capacitance C
G
and a gate bias supply
64
. The gate bias supply
64
includes a first electrode coupled to the gate
62
and a second electrode coupled to one side of the s
Ahn Kie Y.
Forbes Leonard
Ho Hoai
Micro)n Technology, Inc.
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