Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-06-24
2002-04-23
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C360S053000, C360S065000
Reexamination Certificate
active
06378107
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a digital signal reproducing apparatus being adaptable to a use of Viterbi decoding such as video tape recorders and optical disk drives. More particularly, the invention relates to a digital signal reproducing apparatus wherein equalizing references of a differential system and an integrating system are added in a predetermined ratio for decisions of maximum likelihood, or the distances (i.e., branch metrics) from respective amplitude reference values based on the equalizing references of the differential system and an integrating system are added in a predetermined ratio for a binary discrimination, thereby to improve the discriminating accuracy degraded by noise.
BACKGROUND ART
In Video tape recorders, optical disk drives or like, a digital signal recorded at a high density is conventionally intended to ensure reliable the reproduction thereof by processing the reproduced signal with Viterbi decoding.
In other words, Viterbi decoding defines “n” states determined by intersymbolic interference, through the use of combinations of the instant preceding input data. Every time the input data are changed, the current “n” states are replaced with the ensuing “n” states to process the changed input data. Specifically, when the intersymbolic interference has a length of “m”, the “n” states are determinedby the preceding (m−1) bits. For example, when the input signal is a digital signal of “1” and “0”, there exists a total of n=2
(m−1)
states.
It is assumed with reference to the “n” states defined above that the level of noise contained in the reproduced signal has a Gaussian distribution and that the value of the reproduced signals corresponding to each noise-free state is regarded as an amplitude reference value. In that case, the likelihood of a transition to each of the “n” states is represented by a value obtained by squaring the difference between an amplitude reference value and an actually reproduced signal and by accumulating the squared values until one of the states is reached. According to the Viterbi decoding, the likelihood values are accumulated for each of possible paths leading from the preceding “n” states to each of the current states. Given the result of the calculations, it is judged that a transition has taken place over the path having the strongest likelihood (i.e., with the smallest accumulated value). With the judgment made, the current “n” states are replaced by the ensuing “n” states, and the hysteresis and likelihood of a discriminated value in each state are updated.
The transitions of maximum likelihood states are detected successively up to a stage where hysteretic records going back several bits in time are merged into a single item of hysteresis. This finalizes the result of signal discrimination so far. As outlined, Viterbi decoding discriminates the reproduced signal by making the most of the signal power of the reproduced signal where the noise superimposed on the reproduced signal is random noise. The Viterbi decoding provides an appreciable improvement of the error rate over the conventional decoding method by which the reproduced signal is compared with a predetermined threshold value for each bit.
Such Viterbi decoding is commonly used to process signals equalized in partial response. Depending on the characteristics of a transmission system in use, either the equalized characteristic of an integrating system such as PR (1, 1; referred to as PR
1
hereinafter) or the equalized characteristic of a differential system such as EPR (Extended Partial Response; 1, 1, −1, −1; referred to as EPR
4
hereinafter) is adapted to partial response equalization.
FIG. 18
is a table showing state transitions of a combination of RLL (Run Length Limited; 1, 7) code with EPR
4
equalization. The RLL (1, 7) code is a coding method whereby at least two logical 1s or 0s always occur continuously (a single logical 1 or 0 will not occur under the coding scheme based on what is known as d=
1
restriction). EPR
4
entails intersymbolic interference in subsequent three bits for each input data item because of PR (1, 1, −1, −1).
In the above combination, the hysteresis of input data of up to three earlier bits determines uniquely the state transition (output) of the subsequently input data. In
FIG. 18
, a[k] denotes input data, and a[k−1], a[k−2] and a[k−3] stand for input data which are one, two and three clock pulses previous to the input data a[k] respectively. A state b[k−1] resulting from the input data a[k−1], a[k−2] and a[k−3] is represented by a symbol S together with respective values of the input data a[k−1], a[k−2] and a[k−3]. For example, when the input a[k] has a value of 0 in a state (S
000
), then an output c[k] with a value of 0 is obtained, and a state b[k] is changed to (S
000
).
According to the RLL (1, 7) code, the states (S
010
) and (S
101
) do not occur under the d=1 restriction. With the two states (S
010
) and (S
101
) excluded, each state b[k−1] is changed to two states corresponding to the 0 or 1 input, whereby six states are taken as a whole. In the case of the RLL (1, 7) code, the output signal c[k] has five amplitude reference values: −2, −1, 0, 1 and 2. These relations are illustrated in a trellis diagram of FIG.
19
.
As shown in the trellis diagram of
FIG. 19
formed by repetitive patterns, the Viterbi decoding method decodes the input signal by accumulating squared values of the difference between an EPR
4
equalized reproduced signal and an EPR
4
equalized amplitude reference value (the difference is made of distances, i.e., branch metrics) and by selecting the path having the smallest accumulated value (metric).
With regard to the equalized characteristic of an integrating system such as PR
1
, a low frequency region tends to be emphasized excessively as shown in FIG.
20
. When the equalized characteristic of such an integrating system is applied to a magnetic recording and reproducing system having difficulty in reproducing DC components, the low frequency region of the latter system is likely to be inordinately emphasized. This results in a deterioration of the accuracy of signal discrimination due to low frequency noise such as cross talk.
With respect to the equalized characteristic of a differential system such as EPR
4
, the low frequency region is suppressed while a high frequency region with an inferior S/N ratio tends to be emphasized, as illustrated in FIG.
21
. when the equalized characteristic of such a differential system is applied to a magnetic recording and reproducing system for high-density (short waveform) recording, the presence of high frequency noise can make it difficult to ensure sufficient accuracy of signal discrimination.
It is appreciated that recording density, for example will be further enhanced when such noise-degraded levels of accuracy in signal discrimination are improved.
Therefore, the present invention is invented to overcome the above deficiencies and disadvantages of the prior art and it is the object thereof to provide a digital signal reproducing apparatus capable of improving noise-degraded levels of accuracy in signal discrimination.
DISCLOSURE OF INVENTION
According to the present invention, there is provided a digital signal reproducing apparatus wherein equalized signals of a differential system and an integrating system are added in a weighted manner to obtain an added equalized signal which is subjected to maximum likelihood decoding, whereby a result of binary discrimination corresponding to an input signal is outputted.
Metrics of the differential system and the integrating system are added using a predetermined weighting factor every transitions corresponding thereto. Then, the calculated metrics are accumulated to obtain likeliho
Baker Stephen M.
Bell Boyd & Lloyd LLC
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