Electrical computers and digital processing systems: memory – Address formation
Reexamination Certificate
2000-07-25
2002-09-24
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
C711S145000, C711S154000, C711S220000
Reexamination Certificate
active
06457113
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a multi-channel signal processing apparatus suitable for use in signal processing implemented on signals on a plurality of channels.
(2) Description of Related Art
When a firmware (signal processing apparatus) for processing signals such as voice signals is developed with a DSP (Digital Signal Processor), it is general that one DSP is assigned to signals on one channel and the processing is implemented since a processing performance of a known DSP has a limitation in processing of only one channel.
In recent years, a processing performance of one DSP is far progressed owing to contrivance and advance of the semiconductor technique and architecture (similar to parallelizing), it is thereby possible to implement processing of a plurality of (multi) channels by one DSP. A DSP capable of such multi-channel processing is used in an apparatus in an infra-system that collectively processes information (channel signals) from a number of terminals such as a base station apparatus in a mobile communication system for portable phones, etc., for example.
To realize such a multi-channel processing DSP (firmware) , it is necessary that signal processing of a certain channel does not affect signal processing of another channel (interchannel interference). In concrete, it is desirable that a memory region that is being used by a certain channel is not doubly used by another channel.
Namely, when realizing a DSP firmware for multi-channel processing, it is necessary to describe (create) a program in consideration of a problem of interchannel interference including a decision on memory allocation for each channel, etc.
On the other hand, processing of each (single) channel is widely distributed as a processor core, which is an established technique because of its easy verification. For this, when implementing multi-channel processing, it is a shorter way to realization of a reliable, efficient program to modify the processing of individual channels as less as possible and implement the same.
When a processor core for single-channel (hereinafter referred to as a single-channel core) is adapted to the multi-channel processing, there can be two kinds of manners as below:
{circle around (1)} copying individual data of each channel (channel's individual data) in a memory region for a single-channel core, then implementing the processing, and restoring (copying-back) a result of the processing to the original region after completion of the processing; and
{circle around (2)} describing a program such that a memory region for a single-channel core can be set for each channel.
However, in the above manner {circle around (1)}, a process of copying and copying-back data of channel's individual data is required when processing of each channel is switched, which leads to degrade of the processing efficiency. In the above manner {circle around (2)}, it is necessary to set a pointer for data access after explicitly referring to a location of channel's individual data at the time of each access to the memory region, leading to a complicated program and degradation of the program efficiency. Such degradation of the program efficiency causes not only an increase of the number of DSPs and an increase of the apparatus cost but also an increase of power consumption when the identical functions are implemented.
In signal processing performed by a DSP, there sometimes exists processing (for example, system processing by interruption or the like) that can be common to every channel without necessity to be implemented for each channel. However, when taking the processing common to every channel into consideration in the above manners {circle around (1)} and {circle around (2)}, it leads to an increase of the number of times of a process of copying and copying-back or a further complicated program.
SUMMARY OF THE INVENTION
In the light of the above problems, an object of the present invention is to provide a multi-channel signal processing apparatus enabling highly-efficient multi-channel signal processing without largely modifying a signal processing program for single-channel.
The present invention therefore provides a multi-channel signal processing apparatus comprising a memory unit, a signal processing unit for single-channel for implementing predetermined signal processing using a memory region of the memory unit according to a signal processing program for single-channel, an address generation unit for single-channel for generating a first memory address for single-channel processing according to the signal processing program, a pointer adding unit for adding a pointer value indicating the head of an unused memory region of the memory unit to the first memory address generated by the address generation unit each time the signal processing in the signal processing unit is completed to generate a second memory address, and an address selecting unit for selecting either the first memory address or the second memory address as a real address for the memory unit.
Therefore, the multi-channel signal processing apparatus according to this invention enjoys the following advantages:
{circle around (1)} Implementation of the multi-channel signal processing is possible using a program for single-channel processing as it is, whereby a reliable, efficient multi-channel signal processing apparatus is realized at a low cost.
{circle around (2)} Since a memory use region in a necessary size is successively arranged for each channel, it is possible to avoid in advance an interference problem of memory use regions unaware of detailed region arrangement (memory allocation) when a program is created even if a size of a memory use region necessary for each channel is different.
{circle around (3)} It is unnecessary to copy and copy-back data as done heretofore, so that there is no decrease of the processing efficiency due to multi-channelization.
{circle around (4)} When processing that is sufficient to be performed commonly to every channel is implemented, a memory address for single-channel generated by the address generation unit is selected as it is as a real address of the memory unit by the address selecting unit, and a memory use region is fixed to an area other than the memory use area for the multi-channel processing. Therefore, it is possible to cope with the processing common to every channel without adding modification to the program for single-channel processing.
The present invention further provides a multi-channel signal processing apparatus comprising a memory unit, a signal processing unit for single-channel for implementing predetermined signal processing using a memory region of the memory unit according to a signal processing program for single-channel, an address generation unit for single-channel for generating a first memory address for single-channel processing according to the signal processing program, and a pointer adding unit for providing a second memory address obtained by adding a pointer value indicating the head of an unused memory region of the memory unit to the first memory address generated by the address generation unit each time the signal processing in the signal processing unit is completed as a real address for the memory unit.
Namely, it is possible to omit the above address selecting unit to use the above second memory address as a real address. In which case, the advantages {circle around (1)} to {circle around (3)} described above are attained with the above pointer value.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
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Fujino Naoji
Kobayashi Noboru
Kurihara Hideaki
Nishida Fumiaki
Fujitsu Limited
Katten Muchin Zavis & Rosenman
Thai Tuan V.
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