Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1999-03-23
2002-01-15
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S108000, C710S110000, C710S120000, C710S120000, C710S120000, C713S401000
Reexamination Certificate
active
06339806
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention pertains to computers and other electronic systems and, more particularly, to such a system that includes a primary serial bus and a plurality of secondary serial buses, and means for coupling the primary serial bus to a selected secondary serial bus.
The Inter-Integrated Circuit or “I
2
C” bus is a well known industry standard serial bus for interconnecting and transferring information between various integrated circuits or “chips” in a computer or other electronic system. The standard I
2
C bus includes two lines, an “SDA” line for transmitting start, address, data, control, acknowledge and stop information, and an “SCL” line that carries the clock.
Briefly, a bus master transmits a start bit followed by 8 bits of address and read/write information. The start bit is unique in that the SDA line transitions from high to low while the SCL line is high. The only other time the SDA line transitions when the clock line is high is during a stop bit, which is a low to high transition of the SDA line when SCL is high. The next 8 bits include 7 address bits and 1 read/write bit. Of the 7 address bits, 4 of these bits are preprogrammed by the chip manufacturer and the remaining 3 bits are typically programmed by the system manufacturer, typically through three inputs on the chip that can be pulled up or down as required. Consequently, because the chip manufacturer pre-programs the most significant 4 bits of a 7 bit address, leaving only 3 programmable address bits for the system manufacturer, a computer or other electronic system is usually limited to having a maximum of 2
3
or 8 of the same type of chip connected to any one I
2
C bus.
Following the transmission of the address and read/write bits, the addressed slave responds with and “ACK” or acknowledge bit. Next, the master transmits 8 bits of data, which is again followed by the transmission of an ACK from the slave. This pattern of 8 data bits followed by an ACK bit can be repeated until all data has been transmitted, or it can be terminated only after one byte of data is transmitted by the transmission of a stop bit following the data acknowledge bit from the slave.
Bus loading is a limitation as to the total number of devices that can be coupled to any one bus. Consequently, because of bus loading, and because of the inability to address more than 8 of the same type of chip on any one I
2
C bus, system manufacturers have previously incorporated more than one I
2
C bus in a system, and they have used two general approaches to interconnecting multiple I
2
C buses.
The first approach is to use multiple primary I
2
C buses, each with its own controller.
The first approach solves the limitations of loading and address availability, but requires extra controllers, which are usually the most expensive device in an I
2
C circuit. In addition, the requirement of running a number of primary I
2
C buses through many connectors and interfaces adds cost and, in some cases, is not possible because of the limited pin count of the connectors and interfaces.
The second approach is to use a primary I
2
C bus multiplexed onto two or more secondary I
2
C buses, but controlled separately from any of the secondary buses. The second approach is an improvement over the first in that it does not require multiple controllers and it is not constrained to run through multiple connectors and interfaces. However, a new complexity arises in that a separate mechanism must be set up to control the multiplexing. Since the primary I
2
C bus is switched in this approach, it must be controlled from a different primary I
2
C bus; otherwise data loss and signal quality degradation will occur. Consequently, the need for more than one primary I
2
C bus limits the benefits of this approach.
Accordingly, the invention described below has all the benefits of the approaches described above, but without any of the aforementioned limitations. In particular, this invention can generate new addresses for each of the secondary serial buses, but it does not require more than one controller or more than one primary serial bus.
SUMMARY OF THE INVENTION
Briefly, the invention is an electronic system that includes a primary I
2
C bus for communicating start bits, address bits, data bits, acknowledgment bits and stop bits over an SDA line of the primary I
2
C bus, wherein a block of data bits is followed by an acknowledgment bit and a stop bit. The system also includes a plurality of secondary I
2
C buses and an expander with a unique I
2
C address. The expander includes a bus port coupled to the primary I
2
C bus, and a plurality of outputs that can be selectively activated. A controller is coupled to the primary I
2
C bus. The controller can activate a selected one of the outputs of the expander by transmitting the unique I
2
C address to the bus port of the expander, followed by the transmission of a predetermined block of data bits. A bus switch includes a bus input coupled to the primary I
2
C bus and a plurality of bus outputs, wherein each of the of secondary I
2
C buses is coupled to a unique one of the bus outputs. The bus switch also includes a plurality of control inputs, such that the primary I
2
C bus can be connected to a unique one of the secondary I
2
C buses in response to the activation of the corresponding control input. A plurality of delay circuits, each one coupled between a unique one of the outputs of the expander and a unique one of the control inputs of the bus switch, delays the activation of the corresponding control input of the bus switch until after an acknowledgment bit and a stop bit have been communicated over the primary I
2
C bus.
In another embodiment, the invention is an electronic system including a primary serial bus for communicating address bits, data bits and control bits over an information line of the primary serial bus, wherein a block of data bits is followed by a control bit. The system also includes a plurality of secondary serial buses, and an expander with a unique address. The expander includes a bus port coupled to the primary serial bus, and a plurality of outputs that can be selectively activated. A controller is coupled to the primary serial bus. The controller selectively activates a selected one of the outputs of the expander by transmitting the unique address to the bus port of the expander, followed by the transmission of a predetermined block of data bits. A bus switch includes a bus input coupled to the primary serial bus and a plurality of bus outputs, wherein each of the secondary serial buses is coupled to a unique one of the bus outputs. The bus switch also includes a plurality of control inputs, such that the primary serial bus can be connected to a unique one of the secondary serial buses in response to the activation of the corresponding control input. A plurality of delay circuits, each one coupled between a unique one of the outputs of the expander and a unique one of the control inputs of the bus switch, delays the activation of the corresponding control input of the bus switch until after a control bit has been communicated over the primary serial bus.
REFERENCES:
patent: 5604918 (1997-02-01), Huijsing et al.
patent: 5696994 (1997-12-01), Pang
patent: 6145102 (2000-11-01), Klein et al.
patent: 6233635 (2001-05-01), Son
patent: 6286073 (2001-09-01), Vegter
Bandholz Justin Potok
Foster, Sr. Jimmy Grant
Muse Richard Jesse
Dharia Rupal
McKinley Martin J.
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