Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-26
2002-05-21
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S202000, C257S365000, C438S574000, C438S579000, C438S182000
Reexamination Certificate
active
06392278
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a field effect transistor (FET) having a reliable gate electrode and, more particularly, to the structure of a FET adapted for use in a short wavelength range such as on the order of millimeters.
(b) Description of the Related Art
Active components such as FETs capable of operating in a shorter wavelength range have increased demands. FETs made of III-V group compound semiconductors have higher operational speeds or operate, in a higher frequency range compared to FETs made of silicon due to a higher travelling speed of electrons in the compound semiconductors. Thus, FETs made of III-V group compound semiconductors such as GaAs, especially MESFETs having Schottky junctions, are developed in these days.
In general, the operational speed of the FET depends on the velocity of the carriers passing just below the gate electrode of the FET. Thus, the pursuit of a higher speed in the FET inevitably leads to reduction of the gate length thereof.
The gate electrode generally assumes a profile of character “T” or mushroom in the cross-section thereof for reduction of the input resistance, wherein the top portion of the gate electrode is thicker or larger compared to the bottom portion where the gate electrode contacts with a semiconductor layer. In addition, the gate electrode may have a width of as large as several hundreds of; micrometers for achieving a higher output power. In this case, the gate electrode is generally divided into a plurality of portions each having a width of 5 to 110 &mgr;m, thereby alleviating the phase delay of the input signal. These portions are arranged in a so-called comb shape, and such FET is called comb-shape FET.
FIG. 1
shows the structure of a conventional comb-shape FET, wherein the dimensions in the figure are not shown to scale. In
FIG. 1
, a rectangular active region
31
is surrounded by an inactive region
32
on a GaAs substrate. The comb-shape gate electrode
33
has a plurality of gate fingers
33
a
extending across the active region
31
in parallel to one another. The proximal ends of the gate fingers
33
a
are coupled to a gate bar
33
b
having a larger width and disposed in the inactive region
32
in the vicinity of the boundary between the inactive region
32
and the active region
31
.
A source ohmic electrode
34
and a drain ohmic electrode
35
are disposed in the active region
31
, sandwiching therebetween each of the gate fingers
33
a
. A source lead
36
is of a comb-shape, and has a source lead bar
36
b
overlying the inactive region
32
and a plurality of source lead fingers
36
a
each extending from the source lead bar
36
b
. A drain lead
37
is of a comb-shape, and has a drain lead bar
37
b
overlying the inactive region
32
and a plurality of drain lead fingers
37
a
each connected to the drain lead bar
37
b
. Each source lead finger
36
a
is in ohmic contact with a corresponding source ohmic electrode
34
, and each drain lead finger
37
a
is in ohmic contact with a corresponding drain ohmic electrode
35
.
FIGS. 2A
to
2
D are sectional views of the FET of
FIG. 1
, showing consecutive steps of fabrication thereof. These figures are taken along line II—II in FIG.
1
.
In fabrication of the MESFET of
FIG. 1
, an n-type GaAs layer
11
acting as a channel layer is grown on a semi-insulating GaAs substrate
10
, followed by growth of an n
+
-type GaAs contact layer
12
thereon. After covering a portion of the n
+
-type GaAs contact layer
12
to be formed as the active region
31
by a first photoresist mask, boron ions, for example, are implanted to form a semi-insulating inactive region
32
for isolation of active regions
31
, as shown in FIG.
2
A.
A second photoresist mask is then formed having an opening for exposing the region in which a gate electrode is to be disposed. The dimensions of the opening are larger than the dimensions of the region at which the gate electrode contacts with the GaAs wafer. By using the second photoresist mask, a dry etching process is conducted to form a recess
14
in the n
+
-type GaAs layer
12
, the recess
14
having a bottom within the top portion of the n-type GaAs layer
11
. A silicon oxide film
15
having a specified thickness is then deposited on the entire surface by using a chemical vapor deposition (CVD) technique. The specified thickness is selected depending on the height of the foot of the mushroom shape;to be formed later.
A third photoresist mask is then formed having an opening for exposing the region at which the gate electrode is to be formed. The dimensions of the opening define the gate length “L”. By using the third photoresist mask, the silicon oxide film
15
is etched to form a groove
16
by using a dry etching technique, as shown in FIG.
2
B.
Thereafter, an etching process is conducted to remove a damage layer formed on the surface of the n-type GaAs layer
11
in the previous step. A sputter-deposition is then conducted to form an underlying layer
18
including a bottom WSi film and a top TiN barrier film, followed by another sputter-deposition of thick Au film
19
and a thin TiN film (not shown). The WSi layer in the underlying layer
18
is used for forming a Schottky characteristic, whereas the TiN film acts as a barrier layer against the overlying Au film
19
of the gate electrode. Subsequently, consecutive ion-milling and reactive ion etching steps are conducted for etching the TiN layer, the Au film
19
and the underlying layer
18
, to form the gate electrode
33
including gate fingers
33
a
each having a mushroom shape, as shown in FIG.
2
C.
The silicon oxide film
15
is then removed by etching, followed by CVD of a gate protective film
20
made of silicon oxide. Then, a fourth photoresist mask is formed having openings corresponding to the source and drain ohmic electrodes
34
and
35
on both sides of each gate finger
33
a
in the active region
31
. The source and drain ohmic electrodes
34
and
35
are then formed after etching and liftoff of the gate protective film
20
by using the fourth photoresist mask. Both the ohmic electrodes
34
and
35
are formed by evaporation of AuGe and Au and a subsequent heat treatment thereof for alloying, as shown in FIG.
2
D. Thereafter, source and drain leads
36
and
37
are formed in ohmic contact with the ohmic electrodes
34
and
35
, followed by formation of passivation film etc. to complete the MESFET of FIG.
1
.
In the MESFET as described above, with the reduction of the gate length “L” down to as low as 0.2 &mgr;m, for example, the stress acting at the interface between the semiconductor layer and the metallic film causes damages, such as peel-off or deformation of the gate fingers
33
a
, in the step of etching of the oxide film and subsequent steps, thereby degrading the fabrication yield of the MESFET. In particular, wet treatments, using supersonic wave for stabilizing the washing and etching effects, incur the peel-off of the gate fingers
33
a
from the semiconductor layer
11
, especially often at the distal ends of the gate fingers
33
a
rather than at the proximal ends. Although the protective film
20
is provided for this purpose, the protection by the protective film
20
is insufficient unless the protective film
20
has a sufficient thickness. A thick protective film
20
however causes an increase of the gate capacitance and thus is undesirable in view of the transistor characteristics. In addition, the. peel-off of the gate finger
33
a
itself may occur before formation of the protective film
20
.
Patent Publication JP-A-5-190573 proposes prevention of the peel-off of the gate fingers. Referring to
FIG. 3
showing the detail of the proposed structure for the MESFET, the gate finger
33
a
extends between the source ohmic electrode
34
and the drain ohmic electrode
35
across the active region
31
. The gate finger
33
a
having a mushroom shape in cross section extends from the gate bar
33
b
and has a pair of lateral projections
33
c
a
Diaz José R.
Lee Eddie
McGinn & Gibb PLLC
NEC Corporation
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