Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
1997-06-20
2002-05-07
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S052000, C710S120000, C711S173000
Reexamination Certificate
active
06385672
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to a device for connecting a computer system to a packet-switched data network, such and more particularly to the design of a system that optimizes utilization of a packet buffer within the device for storing packets in transit between the computer system and the packet-switched data network.
2. Related Art
The advent of computer networking has given rise to a number of devices that connect computer systems to packet-switched data networks, such as the Internet. These devices typically include interfaces to the computer system and the data network, as well as a buffer memory, for buffering packets of data in transit between the computer system and the data network. This buffer memory allows data to be downloaded from a host computer system when the host computer system is able to do so, and subsequently transmitted across the data network when the data network can accommodate a transmission, thereby increasing the overall efficiency of communications by the computer system across the data network.
There are typically two buffers in such a network interface device: a transmit buffer for storing data from the computer system to be transmitted onto the data network, and a receive buffer, for receiving data from the data network to be transmitted to the computer system.
In order to optimize the performance of the buffer memory, it is desirable to achieve the proper balance between memory used for the transmit buffer and memory used for the receive buffer. This is complicated by the fact that the optimal transmit and receive buffer sizes can vary widely between different buses, data networks, and network traffic patterns. It is also desirable to minimize buffer underrun and buffer overrun. Buffer overrun occurs when the buffer becomes overly full before packets can be removed from the buffer. Buffer underrun occurs when the buffer becomes empty and data continues to be transmitted from the empty buffer.
These transmit and receive buffers are typically controlled by a controller, which can take the form of a microprocessor. A microprocessor-based controller can access packets in the transmit and the receive buffers using memory mapping which has the advantage that data in the buffers can be flexibly accessed. However, the speed of accesses to the buffer are limited by the microprocessor speed, and hence can be relatively slow. Microprocessors can also be quite expensive, adding significantly to the cost of a network interface card (NIC).
Network interface devices are typically implemented using separate transmit and receive buffers, which are of a fixed size that cannot be varied to meet the requirements of different buses, data networks and network traffic patterns.
What is needed is a system for flexibly allocating buffer memory in a network interface device between transmit and receive buffers in order to optimize performance for the network interface device across a wide range of buses, data networks and network usage patterns.
Additionally what is needed is a low-cost system for controlling the operation of the buffer memory, that is free from the low performance and the high cost of a microprocessor-based controller.
SUMMARY
The present invention provides a device which facilitates communications between a computer system and a data network by buffering data in transit between the computer system and the data network in a single buffer memory which can be flexibly partitioned into separate transmit and receive buffers. This flexible partitioning allows the relative sizes of the transmit and receive buffers to be optimized across a wide range of buses, data networks and network usage patterns. The transmit and receive buffers are structured as ring buffers within respectively allocated portions of the buffer memory. The buffer memory is controlled by a simple finite state machine controller, which is free from the performance impediments and higher cost associated with a microprocessor-based controller. The present invention also provides support for retransmission of packets that encounter transmission problems such as collisions during transmissions on the data network. The present invention additionally provides the ability to discard incomplete packets.
One embodiment of the present invention is an apparatus for transmitting data between a first communication channel and a second communication channel. The apparatus comprises a first interface, coupled to the first communication channel, and a second interface coupled to the second communication channel. The apparatus also includes a buffer memory, coupled to the first communication channel and the second communication channel, the buffer memory being selectively partitionable so that a portion of the buffer memory of selectable size is allocated to a transmit buffer for buffering data to be transmitted on the first communication channel, and a portion of the buffer is allocated to a receive buffer of selectable size for buffering data received from the first communication channel. The apparatus also includes a controller, coupled to the buffer memory, for controlling data flowing through the transmit buffer and the receive buffer.
According to one aspect of the present invention, the controller does not include a microprocessor.
According to another aspect of the present invention, the apparatus includes a plurality of pointer registers coupled to the buffer memory, for storing pointers for accessing the transmit and receive buffers, and at least one logic circuit coupled to the plurality of registers, for performing arithmetic operations on the plurality of pointer values stored in the plurality of pointer registers.
One embodiment is an apparatus for buffering packet data in first in first out order, comprising: a buffer; a write pointer coupled to the buffer, for pointing to a location where packet data is being written into the buffer; a start of a read packet pointer coupled to the buffer, for pointing to the start of a read packet being read from the buffer, and a read pointer coupled to the buffer, for pointing to a location where packet data is being read from the packet being read, the read pointer being resettable to point back to a location stored in the start of read packet pointer to facilitate retransmission of the read packet when a transmission error takes place.
According to an aspect of this embodiment, the apparatus includes a start of write packet pointer coupled to the buffer, for pointing to the start of the packet being written into the buffer. It also includes resources coupled to the write pointer, for resetting the write pointer to point back to a location stored in the start of write packet pointer, to facilitate discarding of an incomplete packet.
According to another aspect of the present embodiment, the apparatus includes an end of read packet pointer, coupled to the buffer, for pointing to the end of a packet being read; and resources coupled to the read pointer, for comparing the read pointer with the end of read packet pointer, to determine when the packet is completely read.
Another embodiment is as an apparatus for performing pointer arithmetic for a pointer into a buffer, the pointer arithmetic including a pointer incrementing operation that increments a first pointer until it reaches a selectable maximum value and then returns to a starting value, comprising: a first pointer input, for receiving the first pointer; a selectable maximum value input, for indicating a selectable maximum value of the output for purposes of setting the output to the starting value during a pointer increment operation that exceeds the selectable maximum value; an output, for outputting the result of a pointer arithmetic operation, and a logic circuit, coupled to the first input, the selectable maximum value input and the output, which includes circuitry that increments the first pointer to produce the output, such that if the value of the first pointer after incrementing exceeds the selectable maximum value, the output is set to the starting v
Reid Richard S.
Wang Chi-Lie
3Com Corporation
McDonnell Boehnan Hulbert & Berghoff
Portka Gary J.
Yoo Do Hyun
LandOfFree
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