Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-08-07
2002-03-05
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S066000, C257S072000, C257S350000, C257S351000, C257S403000, C257S404000
Reexamination Certificate
active
06353244
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to reduction of power consumption of a thin-film semiconductor circuit constituted of crystalline silicon. The invention also relates to reduction of power consumption of a drive circuit of an active matrix display device that is constituted of crystalline silicon.
The invention also relates to an ion doping technique for a semiconductor material, and a manufacturing method of a semiconductor and a semiconductor device using that ion doping technique.
Further, the invention relates to reduction of a leak current while a thin-film transistor (hereinafter abbreviated as “TFT”) is off.
2. Description of the Related Art
In recent years, extensive studies have been made of the active matrix display device using a liquid crystal. In the active matrix display device, a switching element is provided for each pixel and a signal coming from an image signal line is supplied to each pixel through the corresponding switching element.
Although previously TFTs using an amorphous silicon semiconductor were used as the switching element, in recent years TFTs have been developed which use a crystalline silicon semiconductor (i.e., a silicon semiconductor including crystal components) having a high operation speed.
However, in a TFT using a crystalline silicon semiconductor, the leak current (off-current) that flows when the gate electrode is reversely biased is larger than in a TFT using an amorphous silicon semiconductor.
This phenomenon, which is believed due to the existence of crystal grain boundaries, is the most serious problem, because it deteriorates the characteristics of a crystalline silicon-based circuit constituting an active matrix display device and increases its power consumption.
In the case of an N-channel TFT, when V
GS
(source-gate voltage of the TFT) is negative, a leak current is determined by currents flowing through PN junctions that are formed between a P-type layer that is induced in the surface of a semiconductor thin film and N-type layers of source and drain regions. Because of many traps existing in the semiconductor thin film (particularly in grain boundaries), these PN junctions are incomplete, likely causing a relatively large junction leak current.
The reason why the leak current increases as the gate electrode is negatively biased more deeply is that the carrier concentration of the P-type layer formed in the surface of the semiconductor thin film increases, which lowers the energy barrier height of the PN junction, which in turn causes an electric field concentration, resulting in increase of the junction leak current.
The leak current that is caused by the above mechanism strongly depends on the source-drain voltage; that is, the leak current rises sharply as the voltage applied between the source and the drain of a TFT is increased. For example, in some cases, a leak current with a source-drain voltage of 10 V is more than 10 times, rather than 2 times, larger than that with a source-drain voltage of 5 V.
The above nonlinearity also depends on the gate voltage. In general, the leak current difference between the above two cases is larger when the gate electrode is reversely biased more deeply (in an N-channel TFT, when a larger negative voltage is applied).
Typical examples of products using the active matrix display device include a notebook-type personal computer and a portable information terminal. However, in current models of these products, the active matrix display device is responsible for most of the total power consumption. Therefore, to satisfy the need of long-term driving by a battery, it is now desired to reduce the power consumption of the active matrix display device.
However, even where a peripheral drive circuit of an active matrix display device are constituted of CMOS (complementary metal-oxide-semiconductor) TFTs, large leak currents flow through the P-channel TFTs in an off state, making the power consumption of the entire circuit large.
In the case of a high-resolution, large-screen type active matrix display device, long gate lines of the screen cause a problem that there is a delay until the TFT of a selected pixel is turned on. A wiring resistance R
wire
and a wiring capacitance C
wire
of a gate line are approximated as
R
wire
=&rgr;·L
/(
W·T
)
C
wire
=n
ox
·W·L/H
where
&rgr;: resistivity of a wiring material
L: wiring length
W: wiring width
T: wiring film thickness
n
ox
: dielectric constant of a field oxide film.
A delay t
wire
, which is equal to a time constant R
wire
·C
wire
, is expressed as
t
wire
=&rgr;·n
ox
·L
2
/(
T·H
).
This equation indicates that the signal delay due to a wiring line is proportional to the square of the wiring length.
Conventionally, the signal delay due to a wiring line is prevented by reducing the wiring length of gate lines by providing a gate line drive circuit on both sides of the active matrix display device. However, this measure is not sufficient.
SUMMARY OF THE INVENTION
In view of the above problems, an object of the present invention is to provide a thin-film semiconductor integrated circuit formed on crystalline silicon and, in particular, a peripheral drive circuit of an active matrix liquid crystal display device which circuits are low in power consumption.
Another object of the invention is to provide a pixel-switching thin-film transistor of an active matrix liquid crystal device which transistor can prevent a signal delay due to a wiring line.
A further object of the invention is to provide a method for forming thin-film transistors having different threshold voltages (V
th
) on the same substrate.
As described above, the leak current in a CMOS circuit as a thin-film semiconductor integrated circuit formed on crystalline silicon can be reduced by decreasing the source-drain voltage.
To this end, according to the invention, a P-channel TFT and an N-channel TFT are connected to the respective source electrodes of a P-channel TFT and an N-channel TFT of a CMOS circuit. The threshold voltages of the additional P-channel and N-channel TFTs are made higher than those of the TFTs of the CMOS circuit. Thus, by making the additional P-channel and N-channel TFTs in an off state, the CMOS circuit can be separated from a power supply when it is not in use.
Since the TFTs of the CMOS circuit are lower, the leak current of the CMOS circuit is reduced. Thus, the power consumption of an integrated circuit constituted of thin-film transistors can be reduced.
According to another aspect of the invention, pixel TFTs are constructed such that the threshold voltage of each TFT is determined in consideration of a voltage drop due to a wiring resistance of a gate line of an active matrix display device. That is, the TFTs are constructed such that a TFT more distant from a gate line drive circuit has a lower threshold voltage. As a result, the gate voltage of a pixel TFT that is about to be driven is lower than in the conventional case. Therefore, the wiring capacitance of a gate line can be shortened, so that pixel TFTs distant from the gate line drive circuit can be turned on in shorter time than in the conventional case.
A description will be made of a method for making the threshold voltages of a plurality of thin-film transistors formed on the same substrate different from one another, to realize the above-described configurations.
In recent years, it has been attempted to dope the channel region of a thin-film transistor (TFT). In the following, this technique is called “channel doping.”
The channel doping enables control of V
th
(threshold voltage). Although inherently V
th
should be 0 V (actually, I
D
(drain current) approximately has a minimum value when V
G
(gate voltage) is 0 V), it may deviate much from 0 V when a semiconductor material is processed to enhance its crystallinity or improve its uniformity. Other factors may also deviate V
th
from 0 V. In any case, V
th
can be restored to about 0 V by proper channel doping.
Whether an N-type dopant (a doped semiconductor exhibits N-type
Kusumoto Naoto
Ohnuma Hideto
Tanaka Koichiro
Yamazaki Shunpei
Loke Steven
Semiconductor Energy Laboratory Co,. Ltd.
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