Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-10-30
2002-04-16
Baderman, Scott T. (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S030000, C714S732000, C714S733000
Reexamination Certificate
active
06374370
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to microprocessor testing, and more particularly to a system and method for on-chip debug support and performance monitoring for microprocessors and microprocessor systems.
BACKGROUND
It has become very difficult to diagnose failures in and to measure the performance of state-of-the-art microprocessors. This is because modern microprocessors not only run at very high clock speeds, but many of them also execute instructions in parallel, out of program order and speculatively. Moreover, visibility of the microprocessor's inner state has become increasingly limited due to the complexity of the microprocessors and to practical constraints on the number of external pads that can be provided on the chip package.
In the past, the traditional failure diagnosis and performance measurement tools have been external logic analyzers and in-circuit emulators. Logic analyzers are capable of monitoring signals on the chip pads and other externally-accessible system signals, capturing the state of these signals and generating triggers based on their states. Unfortunately, logic analyzers must rely solely on externally-accessible signals to accomplish this, not on signals that are internal to the chip itself. In-circuit emulators, on the other hand, are used to mimic the functional characteristics of a new microprocessor in a system environment and to add visibility to certain data values within the microprocessor. But such devices only emulate the functionality of the microprocessor. By their very nature, they cannot give an accurate representation of the performance characteristics of an actual silicon device. Therefore, they are primarily useful only for developing and debugging system software.
By way of background, U.S. Pat. No 5,488,688, issued Jan. 30, 1996, to David R. Gonzales, et al., discloses a digital signal processor with a FIFO buffer configured on-chip to monitor a fixed set of internal bus signals. The FIFO buffer is coupled to a debug controller that is capable of operating in first and second modes. In the first mode, the CPU may be halted on the occurrence of one of four specifically-enumerated event conditions: after an external request; after a hardware breakpoint (occurrence of specific data or address values); after a software breakpoint (execution of a specific CPU instruction); or after a specified number of instructions have beeri executed. In the second mode, only the FIFO buffer is halted on the occurrence of an event condition. In either mode, the user may examine the contents of the FIFO buffer after a halt to determine what flow of software instructions were executed just prior to the event occurrence. An off-chip serial interface is used to communicate with the debug controller and to examine the contents of the FIFO buffer. The serial interface complies with the well-known Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1, “Test Access Port and Boundary Scan Architecture,” also known as the Joint Test Action Group (JTAG) standard. A serial port conforming to this standard will hereinafter be referred to as a test access port or “TAP.”
By way of further background, U.S. Pat. No. 5,418,452, issued May 23,1995, to Norman C. Pyle, discloses an apparatus for testing integrated circuits using time division multiplexing. In order to reduce the number of pins necessary to communicate the signals from on-chip test nodes to an off-chip logic analyzer, Pyle employs a multiplexer on the chip under test and a demultiplexer in the logic analyzer. Each input of the multiplexer is coupled to an on-chip test node, and the multiplexer select lines are driven by counter outputs. By applying an identical set of counter outputs to the select lines of the demultiplexer, Pyle implements a time-division-multiplexed serial communication line between the chip under test and the logic analyzer. Signals from the numerous test nodes in the chip under test are coupled to the communication line in different time slices. The signals are then reconstructed by the demultiplexer in the logic analyzer.
By way of still further background, U.S. Pat. No. 5,473,754, issued Dec. 5, 1995 to Dale E. Folwell, et al., discloses a scheme for enabling an off-chip device to monitor the state of an on-chip 24-bit program counter in real time using an 8-bit port on the chip under test. Folwell assumes that discontinuities in the program counter will occur only in a limited number of situations. He then captures the contents of the program address bus only when one of these conditions occurs, and then sends those contents off chip via the 8-bit port. Because the contents of the program address bus are not captured with every increment of the counter, the volume of data that must be output via the 8-bit port is reduced.
By way of still further background, U.S. Pat. No. 5,317,711, issued May 31, 1994 to Philip A. Bourekas, et al., discloses a scheme for providing off-chip test access to the signals of an on-chip bus that connects an on-chip cache to an on-chip CPU. The signals of the bus are brought out to the chip's external address/data bus when the external address/data bus is not being used for transactions with main memory or peripherals. To accomplish this, reserved pins on the microprocessor are used to control a multiplexer. Depending on the state of the multiplexer's select lines, either the microprocessor's main memory read/write and data lines, or the address that is being provided to the internal cache memory, is coupled to the chip's external address/data bus.
By way of still further background, U.S. Pat. No. 4,910,417, issued Mar. 20, 1990 to Abbas El Gamal, et al., discloses an improved user-programmable interconnect architecture for logic arrays. Specifically, Gamal uses existing row-column selecting logic in combination with an output multiplexer for coupling user-selectable internal circuit nodes to a particular external chip pad for testing. Additionally, latches are provided for each chip input pin so that, with the assertion of an external signal, all chip inputs may be frozen. Then, the row-column select circuitry and output multiplexer may be used to probe nodes within the chip using the latched inputs as stimulus.
While the above structures are useful for the particular purposes for which they are proposed, they fall far short of teaching or suggesting a comprehensive structure for debugging and monitoring the performance of a state-of-the-art microprocessor or microprocessor system.
Adequate debugging and monitoring of a microprocessor or microprocessor system is further exacerbated by the recent trend to place memory devices of the microprocessor system on-chip with the microprocessor and other chip circuitry. As IC fabrication technology has evolved to the sub-micron level, as evidenced by devices fabricated using a 0.25-micron or even smaller fabrication process, it has become possible to place large memory arrays, such as random access memories (RAMs), static random access memories (SRAMs), and cache RAMs, entirely on-chip with the microprocessor and other circuitry. On-chip memory arrays provide the advantage of direct communication with the CPU without the need for I/Os to external pins.
In spite of the advantages of placing memory arrays on-chip, there are concerns with how to accomplish testing of on-chip memory arrays. On-chip memory arrays, which may account for a large portion,.even a majority, of the total die area of a chip, are much harder to control and observe than their discrete predecessors, making it difficult to use traditional external tester equipment and hardware to test, screen, characterize, and monitor on-chip arrays. Visibility into how on-chip memory arrays function is severely limited by the placement of the array-chip interface, such as the interface between a memory array and a CPU core of a microprocessor chip, for instance, on-chip.
Prior methodologies for testing on-chip memory arrays include both Built-In-Self-Test (BIST) and Direct Access Testing (DA
Bockhaus John W
Fleischman Jay
Baderman Scott T.
Hewlett--Packard Company
LandOfFree
Method and system for flexible control of BIST registers... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for flexible control of BIST registers..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for flexible control of BIST registers... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2852167