Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-08
2002-03-19
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000, C257S317000, C257S321000, C257S322000
Reexamination Certificate
active
06359303
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a non-volatile semiconductor memory device, and more particularly to a split gate flash memory with a virtual ground array, wherein impurity diffusion layers are used as bit lines, and a method of fabricating the same.
In Japanese laid-open patent publication No. 2-292870, one conventional structure of the split gate flash memory is disclosed, which will be described in detail with reference to
FIGS. 1A and 1B
.
FIG. 1A
is a fragmentary plane view illustrative of a first conventional split gate flash memory with the virtual ground array.
FIG. 1B
is a fragmentary cross sectional elevation view illustrative of a first conventional split gate flash memory with the virtual ground array taken along an A-A′ line of FIG.
1
A.
Field oxide layers
125
are provided on a surface of a semiconductor substrate
111
so that the field oxide layers
125
extend in parallel to each other and to a first direction. Under the field oxide films
125
, n-type impurity diffusion layers
123
d
and
123
s
are provided commonly to a plurality of memory cells so that the n-type impurity diffusion layers
123
d
and
123
s
are buried diffusion layers are used for bit lines and source lines. The buried diffusion layer
123
d
forms a drain region. The buried diffusion layer
123
s
forms a source region. A channel region is defined between the buried diffusion layer
123
d
as the drain region and the buried diffusion layer
123
s
as the source region. A gate insulation film is provided, which extends over a half region of the channel region closer to the drain region. A floating gate
115
is provided with extends on the gate insulation film so that the floating gate
115
is positioned over the half region of the channel region and over a part of the field oxide film
125
. An insulation film is provided which extends over a source side half region
114
of the channel region and over the floating gate
115
. A control gate
129
is provided which extends on the insulation film so that the control gate
129
is positioned over the floating gate electrode
115
and the source side half region
114
. The control gate electrode
129
is stripe-shaped. The control gate electrode
129
is used as a word line. Data writing operation is made by injection of hot electrons into the floating gate electrode
115
. Data erasing operation is made by drawing electrons from the floating gate electrode
115
by F-N tunnel current from the floating gate electrode
115
to an erasing gate electrode
141
.
In the above structure, boron doped high impurity regions
127
are provided under a half of the drain region
123
d
and a half of the source region
123
c
, so that edges of the boron doped high impurity regions
127
are adjacent to the bottoms of the gate insulation film under the floating gate electrode
115
. The boron doped high impurity regions
127
causes a source-drain electric field concentration in the boron doped high impurity regions
127
in order to increase the efficiency of hot electron injection.
FIGS. 2A through 2E
are fragmentary cross sectional elevation views illustrative of sequential steps of fabricating the conventional flash memory shown in
FIGS. 1A and 1B
.
With reference to
FIG. 2A
, a nitride layer
151
and a photo-resist mask
166
are formed over a surface of a semiconductor substrate
111
before boron is ion-implanted through stripe-shaped openings
154
into surface regions of the semiconductor substrate
111
so as to form p+-type regions
161
.
With reference to
FIG. 2B
, after the photo-resist mask
166
has been removed, the nitride layer
151
is used as a mask for carrying out an ion-implantation of arsenic through stripe-shaped openings
153
to form n+-type regions
157
.
With reference to
FIG. 2C
, field oxide films
125
are formed in the openings
153
, whereby concurrently diffusions and activation of impurities in the p+-type regions
161
and the n+-type regions
157
are caused thereby to form buried diffusion layers
123
as the n-type source and drain regions and p+-type diffusion regions
127
. After the nitride layer
151
is removed, then a surface of the substrate is subjected to an oxidation to form a gate oxide film
117
.
With reference to
FIG. 2D
, a polysilicon film is entirely deposited for subsequent patterning the polysilicon film to form a floating gate
115
before an inter-layer insulator is then formed.
With reference to
FIG. 2E
, a polysilicon film is entirely deposited for subsequent patterning the polysilicon film to form a control gate
129
and then further an erasing gate not illustrated is formed to complete the flash memory.
In accordance with the above structure of the flash memory, if a degree of integration of the memory is low, then the p+-type region
127
is formed only under the floating gate side of the buried diffusion layer, thereby allowing an efficient hot electron injection. However, if the integration degree is increased and a scaling down of individual elements of the memory is required, then the width of the buried diffusion layers
123
d
and
123
s
is made narrower. Further, boron of the p+-type diffusion region
127
is likely to be diffused as compared to arsenic. For those reasons, p+-type diffusion regions may be formed under the other half side of the buried diffusion layers
123
d
and
123
s
. This problem is easily caused by a slight variation in alignment under the scaled down condition.
FIG. 3
is a fragmentary cross sectional elevation view illustrative of the flash memory structure, where the p+-type diffusion layers are extensively diffused.
It is further required to use different masks for the boron ion-implantation and the arsenic ion-implantation whereby the number of the necessary steps are increased.
FIGS. 4A through 4G
are fragmentary cross sectional elevation views illustrative of another conventional method of fabricating a flash memory which is suitable for scaling down requirement.
With reference to
FIG. 4A
, field oxide regions not illustrated are formed on a p-type silicon substrate
21
before a silicon oxide layer
22
having a thickness of 300 nanometers is formed by a chemical vapor deposition method.
With reference to
FIG. 4B
, a photo-lithography method and a subsequent dry etching method are used to form stripe-shaped openings
23
in the silicon oxide layer
22
.
With reference to
FIG. 4C
, a silicon oxide film is deposited by a chemical vapor deposition for subsequent etch-back process to form side wall oxide films
24
on vertical walls of the stripe-shaped openings
23
. The silicon oxide layer
22
and the side wall oxide films
24
are used as a mask to carry out an ion-implantation of arsenic at an acceleration energy of 40 keV and a dose of 4E15 cm
−2
. The side wall oxide films
24
allow further size down the wide of the stripe-shaped openings beyond the limitation of the photo-lithography technique.
With reference to
FIG. 4D
, an anneal is carried out in a nitrogen atmosphere at a temperature of 950° C. for 20 minutes for activation of the arsenic ions to form impurity diffusion layers
28
s
and
28
d
. Those impurity diffusion layers serve as bit line and source line which are common to a plurality of memory cells. Thereafter, the silicon oxide film
22
and he side wall oxide films
24
are removed, and then a gate oxide film
26
is formed.
With reference to
FIG. 4E
, a photo-resist not illustrated and having openings only memory cell regions is formed before an ion-implantation of boron is carried out at an acceleration energy of 50 keV and a dose of 3E13 cm
−2
.
With reference to
FIG. 4F
, a polysilicon is deposited and then the polysilicon is patterned to form floating gates
30
. Those floating gates
30
are used as masks for carrying out an ion-implantation of arsenic at an acceleration energy of 100 keV and a dose of 4E13 cm
−2
.
With reference to
FIG. 4G
, a polysilicon film is deposited before patterning the same t
Crane Sara
NEC Corporation
Tran Thien F
Young & Thompson
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