High-speed stacked capacitor in SOI structure

Details High-speed stacked capacitor in SOI structure High-speed stacked capacitor in SOI structure

2000-01-03

2002-04-30

Flynn, Nathan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C438S386000, C438S243000, C438S238000, C438S239000, C438S399000

Reexamination Certificate

active

06380578

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device comprising a capacitor having large capacity and low impedance characteristics, and more particularly to a trench type capacitor formed in an SOI (Silicon On Insulator) substrate and a method for manufacturing the trench type capacitor.
2. Description of the Background Art
In a circuit performing a high-speed operation, noises are made by switching a current at a high speed. Such noises are caused by the existence of a parasitic inductance, a parasitic capacitance and a parasitic resistance in each element of the circuit.
In order to reduce the noises, a capacitor having a large capacity and a low impedance is often provided between a DC voltage source such as Vcc and a ground. However, the parasitic resistance existing in an electrode portion of the capacitor hinders the noises from being reduced. In a chip in which an operation is performed in response to a minute signal and an analog circuit and a digital circuit are provided together, particularly, such noises cause serious problems. Accordingly, it is desirable that the capacitor should have a smaller parasitic resistance.
In the case where a capacitor is to be manufactured on a semiconductor substrate, a MOS capacitor or a pn junction capacitor has conventionally been employed.
The MOS capacitor is an element constituting a capacitor by using a MOS gate formed on a semiconductor substrate and an active region formed in the semiconductor substrate. The MOS capacitor is classified into an inversion type and a storage type. The inversion type MOS capacitor is an element having the same structure as the structure of a MOSFET, and designates an element of such a type that a channel layer and a gate electrode in the MOSFET act as both electrodes of the capacitor. On the other hand, the storage type MOS capacitor is an element having such a structure that a MOS gate is formed on an active region provided in a semiconductor substrate, and designates an element of such a type that a gate electrode and the active region act as both electrodes of the capacitor.
Moreover, the pn junction capacitor is an element utilizing a junction capacitance of a pn junction constituted by p-type and n-type active regions formed in the semiconductor substrate.
In the inversion type MOS capacitor, however, a resistance of an inversion layer acting as an electrode is very high, for example, 5 k&OHgr;/□ or more. Therefore, big noises are made during a high-frequency operation. Moreover, in the case where the storage type MOS capacitor is to be formed on an SOI substrate, an active region cannot be formed thickly because an SOI layer provided on a buried oxide film layer (hereinafter referred to as a BOX (Buried Oxide) layer) has a small thickness. Therefore, a parasitic resistance in the active region acting as an electrode has a great value. Furthermore, in the case where the pn junction capacitor is to be formed on the SOI substrate, a parasitic resistance has a great value because an SOI layer has a small thickness in the same manner as the storage type MOS capacitor.
For this reason, a stack type capacitor shown in
FIG. 39
has been devised. FIG.
39
is a sectional view showing a memory cell portion and a peripheral circuit portion of a DRAM. A stack type capacitor
65
is employed for the memory cell portion. The memory cell portion comprises a plurality of memory cells. In each memory cell, a MOS transistor constituted by a MOS gate structure including a gate insulating film
54
and a gate electrode
55
and active regions
52
and
53
formed in a semiconductor substrate
50
and the stack type capacitor
65
connected to the active region
53
through a contact plug
58
make a set. The stack type capacitor
65
is constituted by a first electrode
63
connected to the contact plug
58
, a dielectric film
62
and a second electrode
64
.
Such a stack type capacitor
65
does not have an electrode thereof formed in the semiconductor substrate
50
. Therefore, the electrode can have an optional shape, thereby reducing a resistance value. Accordingly, if the stack type capacitor is formed on the SOI substrate, it is possible to eliminate the problem of a parasitic resistance generated by forming an electrode on an SOI layer.
In order to form the electrode of the stack type capacitor
65
to have an optional shape, however, attention should be paid such that the electrode is not short-circuited with a bit line
59
(which is shown in a broken line because it is present on a section other than a section of FIG.
39
). For this reason, the stack type capacitor
65
is often formed in a high position seen from a surface of the semiconductor substrate
50
.
If the stack type capacitor
65
is formed in a high position, the following drawbacks are caused. For example, in the case where the second electrode
64
of the stack type capacitor
65
and a wiring
66
in the peripheral circuit portion are to be formed at the same time, a conductive material is formed on the dielectric film
62
and an interlayer insulating film
57
and is then subjected to patterning. However, in the case where the second electrode
64
and the wiring
66
are to be patterned by using a photolithography technique, there is a possibility that a difference Y in height between the memory cell portion and the peripheral circuit portion might exceed a depth of focus of a lens (an index indicating an allowable range of focus). If the difference Y in height exceeds the depth of focus, there is a possibility that either or both of the second electrode
64
and the wiring
66
might be subjected to the patterning in a blurred state, thereby obtaining no design dimension.
Moreover, in the case where the wiring
66
is to be formed simultaneously with the formation of the bit line
59
and the second electrode
64
is to be formed simultaneously with the formation of a wiring
67
in order to avoid the problems of the depth of focus, an aspect ratio of a contact plug
67
a
of the wiring
67
is increased. Consequently, it is hard to form a via hole for the contact plug
67
a
and to bury a conductive material in the via hole.
There has been devised a trench type capacitor having such a structure that a capacitor is not formed on a semiconductor substrate but is fabricated in the semiconductor substrate differently from the stack type capacitor.
FIG. 40
is a sectional view showing the prior art described in U.S. Pat. No. 5,759,907 as an example of the trench type capacitor.
FIG. 40
illustrates a trench type capacitor constituted by a dielectric film
119
buried in a trench
118
, an SOI layer
117
and an impurity implantation region
116
which act as a first electrode, and a polysilicon
120
acting as a second electrode. According to this technique, the trench
118
is formed deeply to reach a semiconductor substrate
110
through a BOX layer
111
and the SOI layer
117
. Therefore, a contact area of each electrode and the dielectric film can be increased and a large capacity can be implemented. Moreover, the impurity implantation region
116
acting as the first electrode and the polysilicon
120
acting as the second electrode can be formed thickly or largely. Thus, the problem of a parasitic resistance can be restrained.
In the case where a rays enter the semiconductor substrate
110
to generate a large number of electron—hole pairs in the trench type capacitor shown in
FIG. 40
, their electric charges move to a DC voltage source or a ground through the impurity implantation region
116
, the polysilicon
120
in a trench
118
a
and a metal wiring
125
. Consequently, there is a problem in that a fluctuation in a source voltage is caused. In other words, a tolerance to soft errors is small. For example, when neutron rays are irradiated on a very small amount of boron
10
B present in BPSG to be used as an interlayer insulating film, the boron
10
B generates a rays having a low energy of 1 MeV or less so that the soft errors are made. The maximum quan

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