Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-11-22

2002-09-10

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S189011, C365S063000, C365S230010, C365S230030, C365S230060, C365S202000

Reexamination Certificate

active

06449198

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device provided with a plurality of memory cells and data transmission line pairs.
2. Description of the Background Art
Conventionally, a synchronous DRAM (hereinafter referred to as SDRAM) can select one of the three word configurations: x4, x8, and x16. These x4, x8, and x16 word configurations respectively allow simultaneous inputting/outputting of 4 bits of data, 8 bits of data, and 16 bits of data.
In addition, an SDRAM allows the so-called multi-bit test (hereinafter referred to as MBT) that permits the reduction in the testing time and an increase in the number of chips tested at the same time. With MBT, a plurality of memory cells (for instance, four memory cells) can be tested for normalcy via one data input/output pin.
FIG. 24
is a block diagram showing a main portion of such an SRAM. In
FIG. 24
, SDRAM includes data buses DB
0
to DB
3
and DB
6
, selectors
151
a
to
151
d,
write data amplifiers (hereinafter referred to as WD amplifiers)
152
a
to
152
d,
write buffers
153
a
to
153
d,
and global IO line pairs GIO
0
to GIO
3
.
Selectors
151
a
to
151
d
connect data bus DB
2
to WD amplifiers
152
a
to
152
d
during a write operation in x4 configuration, and connect data bus DB
0
to WD amplifiers
152
a
and
152
b
and connect data bus DB
2
to WD amplifiers
152
c
and
152
d
during a write operation in x8 configuration. Moreover, selectors
151
a
to
151
d
connect data buses DB
0
to DB
3
respectively to WD amplifiers
152
a
to
152
d
during a write operation in x16 configuration, and connect data bus DB
2
to WD amplifiers
152
b
and
152
d
and connect data bus DB
6
to WD amplifiers
152
a
and
152
c
during MBT.
WD amplifiers
152
a
to
152
d
are respectively activated in response to signals CBS
0
to CBS
3
attaining the logic high or “H” level or the active level, amplify the data provided from outside via data buses DB
0
to DB
3
and DB
6
, and apply the amplified data to write buffers
153
a
to
153
d.
Write buffers
153
a
to
153
d
respectively transmit the data provided from WD amplifiers
152
a
to
152
d
to global IO line pairs GIO
0
to GIO
3
.
During a write operation in x4 configuration, one of signals CBS
0
to CBS
3
(for instance, CBS
0
) attains the “H” level or the active level, and the data provided to data bus DB
2
from outside is transmitted to global IO line pair GIO
0
via selector
151
a,
WD amplifier
152
a,
and write buffer
153
a.
The data transmitted to global IO line pair GIO
0
is written into a selected memory cell.
During a write operation in x8 configuration, one of signals CBS
0
and CBS
1
(for instance, CBS
0
) and one of signals CBS
2
and CBS
3
(for instance, CBS
2
) attain the “H” level or the active level, and the data provided to data bus DB
0
from outside is transmitted to global IO line pair GIO
0
via selector
151
a,
WD amplifier
152
a,
and write buffer
153
a,
while the data provided to data bus DB
2
from outside is transmitted to global IO line pair GIO
2
via selector
151
c,
WD amplifier
152
c,
and write buffer
153
c.
The data transmitted to global IO line pairs GIO
0
and GIO
2
are respectively written into the two selected memory cells.
During a write operation in x16 configuration, signals CBS
0
to CBS
3
all attain the “H” level or the active level, and the data provided to data buses DB
0
to DB
3
from outside are transmitted to global IO line pairs GIO
0
to GIO
3
via selectors
151
a
to
151
d,
WD amplifiers
152
a
to
152
d,
and write buffers
153
a
to
153
d,
respectively. The data transmitted to global IO line pairs GIO
0
to GIO
3
are respectively written into the four selected memory cells.
During a write operation in MBT, signals CBS
0
to CBS
3
all attain the “H” level or the active level, and the data provided to data bus DB
2
from outside is transmitted to global IO line pairs GIO
1
and GIO
3
via selectors
151
b
and
151
d,
WD amplifiers
152
b
and
152
d,
and write buffers
153
b
and
153
d,
while the data provided to data bus DB
6
from outside is transmitted to global IO line pairs GIO
0
and GIO
2
via selector
151
a
and
151
c,
WD amplifiers
152
a
and
152
c,
and write buffers
153
a
and
153
c.
The data transmitted to global IO line pairs GIO
0
to GIO
3
are respectively written into the four selected memory cells.
In addition, the SDRAM includes preamplifiers
154
a
to
154
d,
a CAS latency shifters (hereinafter referred to as CL shifters)
155
a
to
155
d,
selectors
156
a
to
156
d
and
158
a
to
158
d,
and read data buffers (hereinafter referred to as RD buffers)
157
a
to
157
d.
Preamplifiers
154
a
to
154
d
are respectively activated in response to signals PAE
0
to PAE
3
attaining the “H” level or the active level, and amplify the data signals read out to global IO line pairs GIO
0
to GIO
3
. CL shifters
155
a
to
155
d
respectively delay the output signals from preamplifiers
154
a
to
154
d
by one clock cycle.
During a read operation in x4 configuration, selectors
156
a
to
156
d
apply to RD buffer
157
c
the data provided via CL shifter
155
a
from one preamplifier (for instance
154
a
) of preamplifiers
154
a
to
154
d
selected by signals PAE
0
to PAE
3
. During a read operation in x8 configuration, selectors
156
a
to
156
d
apply to RD buffer
157
a
the data provided via CL shifter
155
a
from one preamplifier (for instance
154
a
) of preamplifiers
154
a
and
154
b
selected by signals PAE
0
and PAE
1
, and apply to RD buffers
157
c
to the data provided via CL shifter
155
c
from one preamplifier (for instance l
54
c
) of preamplifiers
154
c
and
154
d
selected by signals PAE
2
and PAE
3
. During the read operations in x16 configuration and in MBT, selectors
156
a
to
156
d
respectively apply to RD buffers
157
a
to
155
d
the data provided via CL shifters
155
a
to
155
d
from preamplifiers
154
a
to
154
d.
Selectors
158
a
to
158
d
couple RD buffers
157
a
to
157
d
to data buses DB
0
to DB
3
during a normal read operation, and couple RD buffers
157
a
to
157
d
respectively to data buses DB
6
, DB
2
, DB
6
, and DB
2
during a read operation in MBT.
RD buffers
157
a
to
157
d
respectively drive data buses DB
0
to DB
3
according to data provided from selectors
156
a
to
156
d
during a normal read operation, respectively drive data buses DB
6
, DB
2
, DB
6
, and DB
2
during a read operation in MBT.
During the read operation in x4 configuration, one of signals PAE
0
to PAE
3
(for instance, signal PAE
0
) attains the “H” level or the active level, and the data read out on a global IO line pair (in this case, GIO
0
) is transmitted to data bus DB
2
via preamplifier
154
a,
CL shifter
155
a,
selector
156
c,
RD buffer
157
c,
and selector
158
c.
The data transmitted to data bus DB
2
is output to the outside.
During the read operation in x8 configuration, one of signals PAE
0
and PAE
1
(for instance, PAE
0
) attains the “H” level or the active level, and the data read out on a global IO line pair (in this case, GIO
0
) is transmitted to data bus DB
0
via preamplifier
154
a,
CL shifter
155
a,
selector
156
a,
RD buffer
157
a,
and selector
158
a,
and one of signals PAE
2
and PAE
3
(for instance, PAE
2
) attains the “H” level or the active level, and the data read out on a global IO line pair (in this case, GIO
2
) is transmitted to data bus DB
2
via preamplifier
154
c,
CL shifter
155
c,
selector
156
c,
RD buffer
157
c,
and selector
158
c.
The data transmitted to data buses DB
0
and DB
2
are output to the outside.
During the read operation in x16 configuration, signals PAE
0
to PAE
3
all attain the “H” level or the active level, and the data read out on global IO line pairs GIO
0
to GIO
3
are respectively transmitted to data buses DB
0
to DB
3
via preamplifiers
154
a
to
154
d,
CL shifters
155
a
to
155
d,
selectors
156
a

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