DRAM access method and a DRAM controller using the same

Details DRAM access method and a DRAM controller using the same DRAM access method and a DRAM controller using the same

1999-02-26

2002-01-01

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S105000, C711S154000, C711S203000, C365S203000, C365S222000, C365S228000

Reexamination Certificate

active

06336162

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to a control for a dynamic random access memory (hereinafter referred to as a DRAM), more specifically to a high speed access method to the DRAM and a DRAM controller for controlling the DRAM.
BACKGROUND OF THE INVENTION
In order to increase a processing speed of a computer system including the DRAM, it is necessary to shorten an access time to the DRAM. A paging method has been used to shorten the access time to the DRAM in the prior art. The paging method is the one in which in the access to the DRAM a row address is fixed after it is once designated (a RAS access) and data is read out in response to a designation of a column address(a CAS address). The paging method has an advantage that the paging method is capable of performing a high speed access because of the less number of RAS access times than those of the so-called RANDOM access method (RAS access mode method) in which the RAS access and the CAS address are performed alternately.
The Japanese Patent Laid Open No. Hei 3-25785 discloses a memory device which uses the conventional paging method.
FIG. 1
shows a flow chart of an access to this memory device. Referring to
FIG. 1
, after starting of the access, the presently accessed row address and the lastly accessed address stored in the register are compared. If both the row addresses coincide with each other, the row address is sent out, and the CAS access is performed. If both the row addresses do not coincide with each other, the row address and the column address are sent out after precharging, and the RAS access and the CAS address are performed.
The access method using the paging method shown in
FIG. 1
enables a high speed access because only the CAS access is performed when the row addresses coincide with each other. However, in this conventional access method, when the row addresses do not coincide with each other, the RAS and CAS accesses must be performed after the precharging. Consequently, when the row addresses do not coincide, the conventional access method inherently involves a drawback that an access operation to the DRAM is delayed by the precharging time rather than in the random access method. That is, it may be said that the paging method is useful only in a local access to the final. Noted that the word “local access” means the one in which the access is performed intensively for a certain address group (area) in the memory.
The memory control circuit which has improved the drawback of the conventional paging method is disclosed in Japanese Patent Laid Open No. Hei 7-84866. In this memory control circuit, a method is disclosed, in which utilizing the localization of the access the possibility of a coincidence of the row address with the lastly accessed row address is predicted at the time when a demand for the access is issued and an access mode is changed.
However, in this case, as a condition for detecting the possibility of the coincidence of the row addresses in the memory access, it is utilized whether access subjects coincide with each other. Here, the access subject is generally called a bus master. Therefore, in this memory control circuit, an access subject number must be newly introduced into a register and a comparison circuit and the like for the access subject number must be additionally provided. Moreover, in the foregoing Japanese Patent Laid Open No. Hei 7-84866, no access method which pays an attention to an access type is referred.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a DRAM access method and a DRAM controller which enables a high speed DRAM access.
Another object of the present invention is to provide a DRAM access method and a DRAM controller which further improve a conventional paging method.
Still another object of the present invention is to provide a novel DRAM access method and a DRAM controller which tracks the localization of a DRAM access and a relation between a DRAM access type and an access mode.
Still further another object of the present invention is to provide a method which forecasts a localization of a DRAM access based on a certain hint, thereby enabling a high speed DRAM access and a DRAM controller.
According to the present invention, there is provided an access method to a DRAM which comprises the steps of detecting an access type to the DRAM; and changing an access mode in response to the detected access type. Here, the word access type means either an instruction access or a data access. Moreover, the word access mode means either a paging mode or a random access mode.
Furthermore, according to the present invention, there is provided an access method to a DRAM which comprises the steps of detecting whether a currently accessed row address and a lastly accessed row address coincide; and changing an access mode in response to an existence of the coincidence of the detected row addresses.
Still furthermore, according to the present invention, there is provided a controller for controlling a DRAM, which comprises means for detecting an access type to the DRAM in response to a signal from a processor; and means for changing an access mode to the DRAM in response to the detected access type.
Still furthermore, according to the present invention, there is provided a controller for controlling a DRAM which comprises means for detecting whether a currently accessed row address and a lastly accessed row address are coincident; and changing an access mode in response to an existence of the coincidence of the detected row addresses.


REFERENCES:
patent: 5265236 (1993-11-01), Mehring et al.
patent: 5651130 (1997-07-01), Hinkle et al.
patent: 5715421 (1998-02-01), Akiyama et al.
patent: 64-59692 (1989-03-01), None
patent: 07-084866 (1995-03-01), None
patent: 7-210456 (1995-08-01), None
patent: 10-49436 (1998-02-01), None
patent: 10-097788 (1998-04-01), None

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