Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output command process
Reexamination Certificate
2000-11-09
2002-03-12
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output command process
C710S071000, C712S227000, C714S030000, C714S034000, C714S035000
Reexamination Certificate
active
06356960
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to microcomputers and computer systems.
BACKGROUND TO THE INVENTION
Single chip microcomputers are known including external communication ports so that the chip may be connected in a network including for example connection to a host microcomputer for use in debugging routines. Such systems are known in which each of the interconnected microcomputer chips has its own local memory. When a debugging routine is determined by a host connected to an integrated circuit microcomputer, problems may arise if normal code used by the microcomputer is unaware of how the host operates.
It is an object of the present invention to provide an improved computer system, and an improved method of operating a microcomputer system, in which external communications obtained from locations off-chip are used for debugging.
SUMMARY OF THE INVENTION
The invention provides a computer system including a microprocessor on an integrated circuit chip comprising an on-chip CPU with a plurality of registers and a communication bus providing a parallel communication path between said CPU and a first memory local to said CPU, said integrated circuit device further comprising a debugging port connected to said bus on the integrated circuit chip and to an external debugging computer device having a second memory, said external debugging device being operable to transmit control signals through said debugging port (a) to stop execution by the CPU of instructions obtained from said first memory (b) to provide from said second memory a debugging routine to be executed by the CPU and (c) to restart operation of the CPU after said routine with execution of instructions from an address determined by said external debugging device, whereby said on-chip CPU is operable with code in said first memory which is independent of said debugging routine.
Preferably said CPU is provided with logic circuitry operable to suspend execution of an instruction sequence by said CPU, said logic circuitry having an address store for holding an instruction location address for use in resuming execution of instructions by the CPU, said logic circuitry being connected to said communication bus whereby the logic circuitry may receive a signal packet from said external computer device through said debugging port.
Preferably said CPU includes an instruction pointer circuit for indicating a next fetch address in execution of an instruction sequence and said address store of said logic circuitry is operable to change the pointer value in said instruction pointer circuit in response to a signal packet from said external computer device.
Preferably said pointer circuit is operable to point to addresses in either of said first or second memories.
The invention includes a method of debugging a computer system which comprises a microprocessor on an integrated circuit chip with an on-chip CPU, a plurality of registers and a communication bus providing a parallel communication path between said CPU and a first memory local to said CPU, said integrated circuit device having a debugging port connected to said bus and to an external debugging computer device having a second memory, said method comprising transmitting control signals from said external debugging device through said debugging port (a) stopping execution by the CPU of instructions obtained from said first memory (b) executing by the CPU a debugging routine provided from said second memory and (c) restarting operation of the CPU after said debugging routine with execution of instructions from an address determined by said external debugging device, whereby said on-chip CPU is operated with code in said first memory which is independent of said debugging routine.
Preferably in response to control signals through said debugging port from said external debugging device, logic circuitry connected to said on-chip CPU operates to suspend execution of an instruction sequence by said CPU, store in an address store for said CPU an instruction location address for use in resuming execution of instructions by the CPU and cause said CPU to resume execution of an instruction sequence determined by said address store after execution of said debugging routine.
Preferably instructions executed by the CPU are determined by a fetch address held in an instruction pointer circuit and said logic circuitry operates in response to a control signal through said debugging port to change the pointer value in said instruction pointer circuit.
Preferably communications on said communication bus are effected in bit parallel format and said debugging port includes translation circuitry which translates packets to a less parallel external format.
Preferably said external format is bit serial.
Preferably communications on said communication bus include request packets for sending from a packet source to a destination, both connected to said bus, and response packets for return from a said destination to a said source.
In one embodiment said first memory holds software for execution by said on-chip CPU and said second memory has software for execution by said on-chip CPU in a debugging routine, said software being transferred from said second memory to said first memory prior to execution by the CPU in a debugging routine.
In some embodiments, a plurality of CPUs are provided on said single integrated circuit chip and a debugging routine is carried out on one of said CPUs as a result of control signals through said debugging port from said external debugging computer device while another of said CPUs on said integrated circuit device executes normal code derived from a first memory local to said CPU.
In some embodiments, a plurality of CPUs are provided on said integrated circuit device each having access to local first memory circuitry, one of said CPUs executing code from said first memory circuitry in order to effect debugging of code executed by another one of said CPUs on the same integrated circuit device.
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Edwards David Alan
Jones Andrew Michael
May Michael David
Lee Thomas
Morris James H.
Park Ilwoo
SGS-Thomson Microelectronics Limited
Wolf Greenfield & Sacks P.C.
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