Coating apparatus – Gas or vapor deposition – With treating means
Reexamination Certificate
1999-07-26
2002-04-16
Dang, Thi (Department: 1763)
Coating apparatus
Gas or vapor deposition
With treating means
C118S7230ER, C118S7230IR, C204S298120, C204S298160
Reexamination Certificate
active
06371045
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a physical vapor deposition device (PVD) for forming a metallic layer on a semiconductor wafer, and more particularly, to a physical vapor deposition device for forming a metallic layer on a semiconductor wafer with an ionized physical vapor deposition process.
2. Description of the Prior Art
Physical Vapor Deposition is a Semiconductor deposition technique using physical methods often employed to deposit a metal layer on a semiconductor wafer. Currently, ionized PVD processing has been developed in order to enhance PVD step coverage and optimize the ability of PVD to fill holes and voids. This process generates metallic ions to deposit a metallic layer and enables the formation of a metallic layer in smaller holes.
Please refer to FIG.
1
.
FIG. 1
is a cross-sectional schematic diagram of the semiconductor wafer
12
after undergoing the ionized PVD process according to the prior art. The semiconductor wafer
12
comprises a plurality of holes that serve as contact holes and via holes needed in the fabrication process. During formation of the metallic layer
14
on the semiconductor wafer
12
using ionized PVD processing in the prior art nphysical vapor deposition device (not shown), neutral metallic atoms are ionized to form positively charged metallic ions
10
and a vertical electric field is formed above the semiconductor wafer
12
. This electric field causes the metallic ions
10
to migrate toward the semiconductor wafer
12
where they become deposited. Thus, a metallic layer
14
forms on the semiconductor wafer
12
and within the holes
16
. The arrow
18
in
FIG. 1
indicates the direction of movement of the metallic ions
10
and the arrow
20
shows the direction of the electric field.
The metallic layer
14
deposited on the semiconductor wafer
12
not only conducts electric current, but also prevents contamination by isolating the semiconductor wafer from subsequently formed matter. It is clear that semiconductor wafer
12
quality is assured only if the metallic layer
14
deposited at each position on the semiconductor wafer
12
achieves a predetermined thickness. In the ionized PVD process of the prior art, the metallic ions
10
move in a downward direction to deposit on the semiconductor wafer
12
. Therefore, the metallic ions more readily deposit on the bottom of the holes
16
than on the vertical-side wall of the holes
16
. In this way, it is difficult to achieve an appropriate thickness of the metallic layer
14
on the vertical-side wall of the holes
16
during the fabrication process.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a physical vapor deposition device for forming a metallic layer on a semiconductor wafer with an ionized physical vapor deposition process on a semiconductor wafer to solve the above mentioned problem.
In a preferred embodiment, the present invention provides a physical vapor deposition device for forming a metallic layer on a semiconductor wafer comprising:
a chamber;
a wafer chuck installed on a bottom end of the chamber for holding the semiconductor wafer horizontally;
a metallic ion generator for generating metallic ions above the wafer chuck;
an electric field generator for forming a vertical electric field above the wafer chuck to guide the metallic ions toward the wafer chuck; and
a magnetic field generator for generating a magnetic field in a direction perpendicular to the moving direction of the metallic ions to create a horizontal moving force over the metallic ions and thus causing the metallic ions to deposit on the semiconductor wafer at a slant angle.
It is an advantage of the present invention that the ionized physical vapor deposition process can form a metallic layer on the vertical-side wall of the holes on the semiconductor wafer meeting the necessary thickness required in the fabrication process.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.
REFERENCES:
patent: 4384933 (1983-05-01), Takasaki
patent: 5659276 (1997-08-01), Miyata
patent: 6023038 (2000-03-01), Van Gogh
Hsieh Chao-Ching
Wang Kun-Chih
Dang Thi
Hsu Winston
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