Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation
Reexamination Certificate
1999-04-22
2002-01-01
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output access regulation
C710S008000, C710S010000, C710S036000
Reexamination Certificate
active
06336156
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to communication systems, and more particularly, to a method and apparatus for decreasing the amount of time required to initialize a network switch in a computer networking system.
2. Description of the Related Art
Modern communication systems, such as computer networking systems or communication networks, provide constant transmission of data between end stations and/or intermediate stations such as routers and signal amplifiers. Computer networking systems, such as packet switched networks (e.g., Ethernet networks), often require transmission of data to a single end station or to multiple end stations within the network. The data originates from a user program, and is segmented into multiple data frames and subsequently transmitted in order to simplify processing and minimize the retransmission time required for error recovery. For example, in a conventional e-mail system, a user may desire to send the same e-mail message to four different users that are connected to the e-mail system. Accordingly, the identical data would be directed to multiple end stations.
Packet switched computer networks typically employ a network switch that receives and forwards frame data to individual and/or multiple end stations. The switch makes forwarding decisions upon receipt of frame data based on information contained in a header of the frame data. For example, if a received frame data is to be transmitted to a number of end stations, the switch must make the forwarding decision to forward the frame data to the ports of the correct end stations. Prior to engaging in routine network activity, most network switches must be properly initialized and configured in order to enable transmission of frame data between the various stations.
Switch initialization and configuration can be accomplished in several ways depending upon the specific system implementation. For example, in certain systems, a Central Processing Unit or (CPU) may be responsible for initializing and configuring the system. Alternatively, the switch may include appropriate hardware for self-initialization.
Significant downtime is typically encountered while waiting for the various subsystems of the switch to be initialized and properly configured. One factor that contributes to this downtime is the manner in which the various sub-systems are scheduled to transmit and receive data. For example, when the switch first becomes operational, there are very few sub-systems that must transmit or receive data. However, most switches simply allocate predetermined time intervals during this period for each sub-system to transmit or receive data. This is particularly wasteful when the majority of sub-systems are idle. Meanwhile, the sub-systems that are active in initializing and configuring the switch are restricted to performing transmit and receive operations only during their prescribed time intervals. Consequently, downtime of the switch is increased because the sub-systems that must perform significant data transfers are not provided with increased time intervals, while the time intervals allocated to the idle sub-systems are wasted. For example, in a typical switch, the sub-system responsible for performing a significant part of initializing the switch may be only allocated ⅕ of the time intervals. However, when the switch is first turned on, ⅗ of the time intervals may be allocated to sub-systems that are idle. Hence, the amount of time required to initialize the switch is significantly increased.
Accordingly, a principal problem associated with network switches is the delay that results when the switch is initialized and configured at startup. Another problem associated with network switches is the amount of bandwidth that is wasted on idle sub-systems during the switch initialization process.
DISCLOSURE OF THE INVENTION
There exists a need for an arrangement capable of quickly and efficiently initializing and configuring a network switch with minimal delay. There is also a need for a low cost arrangement that optimizes the allocation of bandwidth while initializing and configuring a network switch.
These and other needs are addressed by the present invention wherein time slots allocated for accessing an address table by various components of a network switch are reallocated to the component responsible for initializing the address table in order to increase initialization speed of the network switch.
In accordance with one aspect of the present invention, a method of initializing an internal rules checker that makes forwarding decisions for a multiport switch comprises the steps: receiving a first signal that requires initialization of the internal rules checker; increasing, from a nominal value, the number of time slots allocated to an initialization logic of the internal rules checker by a scheduler coupled to the internal rules checker, each time slot corresponding to a prescribed time interval within which data may be transferred to or from the internal rules checker; constructing, by the initialization logic during the increased number of time slots, an address table that stores addresses of source and destination stations that transmit and receive data frames to and from the multiport switch; and decreasing the number of time slots allocated to the initialization logic back to the nominal value after the address table has been constructed. The present method reduces the amount of time required to initialize the multiport switch by temporarily restricting access to the address table by non-essential components during initialization of the multiport switch. The time slots previously allocated to those components are then reallocated to the single component responsible for initializing the address table. Hence, the amount of time required to initialize the multiport switch can be greatly reduced.
In accordance with another aspect of the invention, an apparatus for initializing an internal rules checker that makes forwarding decisions for a multiport switch. The apparatus includes an address table, initialization logic, and a scheduler. The address table stores addresses of source and destination stations that transmit and receive data frames to and from the multiport switch. The initialization logic is used for constructing and initializing the address table upon startup of the multiport switch. The scheduler allocates address table bandwidth in the form of time slots to various components of the multiport switch, including the initialization logic. Each time slot corresponding to a prescribed time interval within which data may be transferred to or from the internal rules checker. In addition, the scheduler is configured to increase the number of time slots allocated to the initialization logic upon startup of the multiport switch, and decreasing the number of time slots allocated to the initialization logic once the multiport switch is initialized. The present arrangement advantageously reduces the amount of time required to initialize the multiport switch by temporarily restricting access to the address table by non-essential components during initialization of the multiport switch. Hence, the amount of downtime experience during initialization can be greatly reduced.
Additional advantages and novel features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following, or may be learned by practice of the invention. The advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 5062035 (1991-10-01), Tanimoto et al.
patent: 5515376 (1996-05-01), Murthy et al.
patent: 6243391 (2001-06-01), Holmquist
patent: 6249521 (2001-06-01), Kerstein
Advanced Micro Devices , Inc.
Lee Thomas
Perveen Rehana
LandOfFree
Increased speed initialization using dynamic slot allocation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Increased speed initialization using dynamic slot allocation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Increased speed initialization using dynamic slot allocation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2848326