Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-07-12
2002-05-07
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S401000, C438S462000, C438S633000, C438S692000
Reexamination Certificate
active
06383930
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for the elimination of copper residue that remains on the surface overlying a wafer alignment mark after copper Chemical Mechanical Polishing of the surface.
(2) Description of the Prior Art
The creation of semiconductor devices in or on the surface of a semiconductor substrate makes extensive use of methods of photolithography for the exposure and patterning of various layers of these devices. The photolithographic process makes use of repeated steps of replicating a required pattern into a semiconductor surface, which in many applications is the surface of a semiconductor substrate. With the continuing increase in device density and device miniaturization, more and more masks are used for the creation of the devices, imposing ever more stringent requirements of accurately aligning the successive masks with respect to each other in order to create well aligned exposures in the layers of photoresist that are used to create the design patterns. Misalignment between layers of photoresist that are used to create device features has a severe negative impact on device yield and must therefore be avoided in a most rigorous manner. The substrate, in or on the surface of which semiconductor devices are created, is first positioned in an exposure tool (the wafer stepper) by using a V-shaped notch in the circumference of the substrate. The wafer is next provided with alignment marks on the surface thereof that are used to align successive exposures that are performed to layers of photoresist that are deposited over the surface of the substrate. The exposure masks that contain the image of the pattern that is to be created on the exposed layer of photoresist that has been deposited over the surface of the substrate also contain alignment marks. By providing exact alignment between the marks provided on the surface of the substrate and the marks provided in the exposure masks, correct alignment between the layers of photoresist that are used for the creation of the semiconductor device can be assured. This alignment is assured by shining a light through the alignment mark of the exposure mask, this light strikes the alignment mark that is on the surface of the substrate from which the light is reflected. The reflected light is intercepted and analyzed by an alignment sensor from which exact alignment between the mark of the exposure mask and the mark of the substrate can be determined.
Current processes make frequent use of copper as an interconnect metal in view of the desirable characteristics of copper such as relatively low cost, ease of processing, stress voiding resistance, low resistivity and resistance against electromigration. In addition, copper finds frequent application as the metal of choice in creating damascene and dual damascene interconnects. The damascene process is being applied for a number of applications, the most commonly applied process being first metal or local interconnects. Where copper provides a challenge is in copper's high susceptibility to oxidation, conventional photoresist processing cannot be used when copper is to be patterned into various wire shapes because the photoresist needs to be removed at the end of the process by heating it in a highly oxidized environment, resulting in oxidation of the exposed copper surfaces. Copper also suffers from high diffusivity in common insulating materials such as silicon oxide and Oxygen-containing polymers. For instance, copper tends to diffuse into polyimide during high temperature processing of the polyimide. This causes severe corrosion of the copper and the polyimide due to the copper combining with oxygen in the polyimide. The corrosion may result in loss of adhesion, delamination, voids, and ultimately a catastrophic failure of the component. A copper diffusion barrier is therefore often required.
The present invention addresses the creation of copper damascene patterns in the surface of a layer of dielectric that overlies an alignment mark. Copper damascene residue that typically remains in place over the surface of the layer of dielectric that overlies the alignment mark is removed by the invention.
U.S. Pat. No. 6,100,158 (Lee et al.) discloses a method for forming a metal layer over an alignment mark.
U.S. Pat. No. 6,087,733 (Maxim et al.), U.S. Pat. No. 6,037,671 (Kepler et al.), U.S. Pat. No. 6,114,215 (Osugi et al.) and U.S. Pat. No. 6,093,640 (Hsu et al.) show related patents, which show alignment marks and metal layers.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a method of removing copper residue from the surface of a layer of dielectric overlying an alignment mark on a semiconductor surface, copper damascene structures having been created in the surface of the layer of dielectric.
Yet another objective of the invention is to equalize the removal rate of a deposited layer of copper from the surface of a layer of dielectric, including the surface region of the layer of dielectric overlying alignment mark and the surface region of the layer of dielectric in which damascene structures are being formed.
A still further objective of the invention is to eliminate copper residue, created during the formation of copper damascene structures, as a source of device failure.
In accordance with the objectives of the invention a new method is provided that affects the polishing rate of the surface of a layer of copper, that has been deposited over the surface of a layer of dielectric. Copper damascene structures have been created in the surface of the layer of dielectric, the layer of dielectric also overlies an alignment mark. The surface of the layer of dielectric that is aligned with the alignment mark is provided with dummy damascene structures, assuring equal polishing rates for active damascene structures and the surface, region of the layer of dielectric overlying an alignment mark. This removes the potential for the accumulation of copper on the surface of the layer of dielectric overlying of the alignment mark.
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patent: 5665655 (1997-09-01), White
patent: 5874778 (1999-02-01), Bhattacharyya et al.
patent: 6037671 (2000-03-01), Kepler et al.
patent: 6087733 (2000-07-01), Maxim et al.
patent: 6093640 (2000-07-01), Hsu et al.
patent: 6100158 (2000-08-01), Lee et al.
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Chen Ying-Ho
Chiou Wen-Chih
Jang Syun-Ming
Shih Tsu
Ackerman Stephen B.
Bowers Charles
Nguyen Thanh
Saile George O.
Taiwan Semiconductor Manufacturing Company
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