Interconnect method and structure for semiconductor devices

Details Interconnect method and structure for semiconductor devices Interconnect method and structure for semiconductor devices

1997-04-16

2002-05-28

Picardat, Kevin M. (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S653000, C438S648000, C438S656000, C438S672000, C438S685000

Reexamination Certificate

active

06395629

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the processing of semiconductor integrated circuit devices, and more particularly to a metal interconnect structure having improved reliability, and a method for making same.
2. Description of the Prior Art
As device feature sizes in semiconductor integrated circuits continue to shrink well below one-half micron, processing flaws which can be ignored for larger feature sizes become an increasing problem. Because conductors are so small, relatively minor flaws resulting from processing can have a significant impact upon the operability of a device.
Metal interconnect is increasingly used in multiple layers in more complex circuits. The very small line width of today's extremely high density devices renders metal conductors susceptible to processing flaws which could be ignored until recently. For example, two types of problems have been noticed with very small line widths in aluminum interconnect lines. The following problems in particular have been identified in connection with the Endura PVD system, but can occur in many different types of equipment.
One such problem is shown in
FIG. 1. A
signal line
10
is formed over a substrate
12
, which is typically an interlevel insulating layer as known in the art. An aluminum layer
14
is formed over the dielectric
12
followed by a TiN anti-reflective coating (ARC) layer
16
. After interconnect pattern and etch to form signal line
10
, shown in cross section of
FIG. 1
, additional processing is performed (not shown). This processing typically includes the deposition and cure of additional interlevel dielectrics, such as spin-on glass (SOG). After such additional processing, voids such as void
18
are often found in the interconnect line
10
. It is believed that such voids are caused by stress relief within the aluminum
14
during subsequent high temperature cure steps. Particularly because of the extremely small size of signal line
10
, voids such as void
18
can have a significant impact upon the overall performance of the device.
A similar problem, with unrelated causes, is illustrated in FIG.
2
. There, interconnect line
20
is formed over interlevel dielectric layer
22
. Aluminum layer
24
is formed over interlevel dielectric, followed by TiN ARC layer
26
. The device is processed in the usual way to form interconnect signal line
20
. Occasionally, TiN layer
26
forms very small cracks
28
, which can lead to the formation of voids
30
within the aluminum
24
. As shown in
FIG. 2
, the size of crack
28
has been exaggerated for clarity.
As is the case with
FIG. 1
, formation of voids such as void
30
can interfere with proper operation of the integrated circuit device, rendering it unusable. It would be desirable to provide an improved manufacturing process, and resulting structure, which reliably solves both of these problems.
SUMMARY OF THE INVENTION
An improved method for fabricating interconnect signal lines in integrated circuits utilizes variations from standard process conditions to relieve stress during formation of metal signal lines. This prevents AlCu stress migration and TiN ARC cracking caused by subsequent high temperature processing. A relatively planar interconnect layer, being one which does not extend through an insulating layer to make contact with an underlying conductor, includes an initial wetting layer of Ti formed over a Ti/TiN layer remaining from earlier processing steps. An AlCu layer is deposited over the Ti at a high temperature with a low deposition rate. Finally, a TiN ARC layer is formed in the usual manner. However, decreased nitrogen flow during deposition lowers the nitrogen content of the ARC layer and prevents later cracking. Deposition conditions for the AlCu layer prevent the formation of voids during subsequent high temperature processing steps.


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Jeong Soo Byun, Kwan Goo Rha, Jae Jeong Kim, and Woo Shik Kim, Formation of a Large Grain Sized TiN Layer Using TiNxthe Epitaxial Continuity at the AI/TiN Interface, and Its Electromigration Endurance in Multilayered Interconnection, 931 Journal of Applied Physics 78 (Aug. 1, 1995), No. 3, Woodbury, NY, pp. 1719-1724.

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