Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of...
Reexamination Certificate
2001-05-15
2002-04-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
C438S509000
Reexamination Certificate
active
06380100
ABSTRACT:
TECHNICAL FIELD
The invention pertains to methods and apparatuses of treating semiconductor wafers, and can have particular applicability to methods of forming antireflective coating materials.
BACKGROUND OF THE INVENTION
Various semiconductor processing procedures involve elevating a wafer above a component to a first predetermined distance for a first treatment, and subsequently lowering the semiconductive wafer relative to a surface of the component for a second treatment. For instance, one process of forming an organic antireflective coating (ARC) involves placing a semiconductive wafer to a first predetermined distance over a hot plate for a first temperature treatment of the wafer, and subsequently lowering the semiconductive wafer directly onto the hot plate for a second temperature treatment. More specifically, a semiconductive wafer coated with a liquid layer of the ARC material is placed over a hot plate to the first predetermined distance. The liquid ARC material is then subjected to a so-called “low temperature bake”. The low temperature bake is typically conducted at from about 80° C. to about 110° C., for a time of from about 30 seconds to about 300 seconds, and at about atmospheric pressure. After the low-temperature bake, the wafer is lowered onto the surface of a hot plate and subjected to a “high temperature bake”. The high temperature bake is typically conducted at from about 120° C. to about 170° C., for a time of from about 30 seconds to about 120 seconds, and at about atmospheric pressure.
A purpose of the low-temperature processing is to remove solvents prior to the subsequent high-temperature processing. If such solvents were not removed, rapid volatilization could occur in the high-temperature processing to cause splattering of ARC material from the semiconductive wafer. A purpose of the high-temperature processing is to densify the deposited ARC material, as well as to drive off any remaining solvents that weren't completely removed by the low-temperature processing.
The above-described low-temperature and high-temperature processings can be conducted with either a single hot plate, or with a pair of hot plates. If a pair of hot plates are utilized, one of the hot plates is dedicated to low-temperature processing, and the other is dedicated to high-temperature processing. The hot plates can have different surface temperatures. Alternatively, both hot plates can have approximately identical surface temperatures, with the difference in processing temperature being achieved by having the wafer elevationally displaced from the first hot plate during the low-temperature processing, and in physical contact with the heated surface of the second hot plate during the high-temperature processing. The elevational displacement of the low-temperature processing can be achieved with a “fixed holdoff” (i.e, with a structure configured to elevate the wafer above the first hot plate by a fixed distance, such structure can comprise, for example, spherical balls held in a groove in the hot plate, or pins extending between the hot plat and the wafer).
If a single hot plate is utilized for both the low and high temperature processings, the semiconductive wafer is generally supported by rods extending through the hot plate and movable relative to the hot plate. The rods are elevated to hold the semiconductive wafer above the hot plate during the low-temperature processing, and then lowered to lay the semiconductive wafer directly upon the hot plate surface during the high-temperature processing.
The single hot plate methods can be advantageous over dual hot plate methods, in that the processing is simpler. Specifically, the dual hot plate methods require a semiconductive wafer transfer step between a first hot plate utilized for low-temperature processing and a second hot plate utilized for high-temperature processing, and such transfer step is eliminated in single hot plate processes. However, single hot plate processes presently suffer a disadvantage in that it is difficult to accurately and reproducibly control the elevational height of a semiconductive wafer during low-temperature processing steps. Specifically, it is found that the support rods extending through a semiconductive wafer do not always hold a semiconductive wafer at the same height above a hot plate heated surface during repeated low-temperature processing. Subtle variations in height can create variations in the temperature at which a semiconductive wafer is processed, which can adversely cause variability amongst treated semiconductive wafers when multiple semiconductive wafers are processed sequentially. Accordingly, it would be desirable to develop alternative semiconductive processing methods wherein the elevational height of a processed wafer can be more tightly controlled.
SUMMARY OF THE INVENTION
In one aspect, the invention encompasses a semiconductor processing apparatus. The apparatus comprises at least one support member having an upper surface for supporting a semiconductor wafer. The apparatus also comprises a component through which the support member extends. The component has a front surface and a back surface, and at least one of the support member and the component is movable relative to the other of the support member and the component. The apparatus includes a mechanical stop associated with one of the support member and the component and not associated with another of the support member and the component. The mechanical stop engages the other of the support member and the component to which it is not associated when the support member upper surface extends above the component to a predetermined distance.
In another aspect, the invention encompasses a semiconductor processing method. At least one support member is provided. The support member has an upper surface for supporting a semiconductor wafer. A component is provided. The support member extends through the component. The component comprises a front surface and a back surface. At least one of the support member and the component is movable relative to the other of the support member and the component such that the support member can support a wafer in an elevated position above the front surface and can be withdrawn into the component to lower the wafer relative to the front surface of the component. A block is provided to be joined to the support member below the component back surface. The block engages the component back surface when the support member upper surface extends above the component to a predetermined distance. The block prevents the support member upper surface from extending beyond the front surface by more than the predetermined distance. The at least one of the support member and the component is moved to elevate the support member relative to the component until the block is engaged against the component back surface. A semiconductor wafer is provided on the elevated support member upper surface. The component is utilized to treat the semiconductor wafer while the semiconductor wafer is on the elevated support member and elevated above the component to the predetermined distance. The at least one of the support member and the component is moved to lower the semiconductive wafer relative to the component. After the semiconductor wafer is lowered, the component is utilized to treat the semiconductor wafer.
REFERENCES:
patent: 4566839 (1986-01-01), Butler
patent: 5566744 (1996-10-01), Tepan
patent: 5834737 (1998-11-01), Hirose et al.
patent: 5998766 (1999-12-01), Mizosaki et al.
patent: 6005386 (1999-12-01), Cadwallader et al.
patent: 6007635 (1999-12-01), Mahawili
patent: 6228740 (2001-05-01), Niroomand et al.
Langley Rodney C.
Rolfson J. Brett
Dang Phuc T.
Nelms David
Wells St. John P.S.
LandOfFree
Semiconductor processing apparatuses, and methods of forming... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor processing apparatuses, and methods of forming..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor processing apparatuses, and methods of forming... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2846695