Chemistry: electrical and wave energy – Apparatus – Electrolytic
Reexamination Certificate
1999-01-15
2002-05-21
Valentine, Donald R. (Department: 1741)
Chemistry: electrical and wave energy
Apparatus
Electrolytic
C204S198000, C204S199000, C204S228700, C204S272000, C204S275100, C204S276000, C205S133000, C205S136000
Reexamination Certificate
active
06391166
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method and apparatus for plating thin films and, more particularly, plating metal films to form interconnects in semiconductor devices.
2. Description of the Prior Art
As semiconductor device features continue to shrink according to Moore's law, interconnect delay is larger than device gate delay for 0.18 &mgr;m generation devices if aluminum (Al) and SiO2 are still being used. In order to reduce the interconnect delay, copper and low k dielectric are a possible solution. Copper/low k interconnects provide several advantages over traditional Al/SiO2 approaches, including the ability to significantly reduce the interconnect delay, while also reducing the number of levels of metal required, minimizing power dissipation and reducing manufacturing costs. Copper offers improved reliability in that its resistance to electromigration is much better than aluminum. A variety of techniques have been developed to deposit copper, ranging from traditional physical vapor deposition (PVD) and chemical vapor deposition (CVD) techniques to new electroplating methods. PVD Cu deposition typically has a cusping problem which results in voids when filling small gaps (<0.18 &mgr;m) with a large aspect ratio. CVD Cu has high impurity incorporated inside the film during deposition, which needs a high temperature annealing to drive out the impurity in order to obtain a low resistivity Cu film. Only electroplated Cu can provide both low resistivity and excellent gap filling capability at the same time. Another important factor is the cost; the cost of electroplating tools is two thirds or half of that of PVD or CVD tools, respectively. Also, low process temperatures (30° to 60° C.) for electroplating Cu are advantageous with low k dielectrics (polymer, xerogels and aerogels) in succeeding generations of devices.
Electroplated Cu has been used in printed circuit boards, bump plating in chip packages and magnetic heads for many years. In conventional plating machines, density of plating current flow to the periphery of wafers is greater than that to the center of wafers. This causes a higher plating rate at the periphery than at the center of wafers. U.S. Pat. No. 4,304,841 to Grandia et al. discloses a diffuser being put between a substrate and an anode in order to obtain uniform plating current flow and electrolyte flow to the substrate. U.S. Pat. No. 5,443,707 to Mori discloses manipulating plating current by shrinking the size of the anode. U.S. Pat. No. 5,421,987 to Tzanavaras discloses a rotating anode with multiple jet nozzles to obtain a uniform and high plating rate. U.S. Pat. No. 5,670,034 to Lowery discloses a transversely reciprocating anode in front of a rotating wafer to improve plating thickness uniformity. U.S. Pat. No. 5,820,581 to Ang discloses a thief ring powered by a separate power supply to manipulate the plating current distribution across the wafer.
All of these prior art approaches need a Cu seed layer prior to the Cu plating. Usually the Cu seed layer is on the top of a diffusion barrier. This Cu seed layer is deposited either by physical vapor deposition (PVD), or chemical vapor deposition (CVD). As mentioned before, however, PVD Cu typically has a cusping problem, which results in voids when filling small gaps (<0.18 &mgr;m) with a large aspect ratio with subsequent Cu electroplating. CVD Cu has high impurity levels incorporated in the film during deposition, requiring a high temperature annealing to drive out the impurities in order to obtain a low resistivity Cu seed layer. As device feature size shrinks this Cu seed layer will become a more serious problem. Also, deposition of a Cu seed layer adds an additional process, which increases IC fabrication cost.
Another disadvantage of the prior art is that the plating current and electrolyte flow pattern are manipulated dependently, or only the plating current is manipulated. This limits the process turning window, because the optimum plating current condition does not necessarily synchronize with optimum electrolyte flow condition for obtaining excellent gap filling capability, thickness uniformity and electrical uniformity as well as grain size and structure uniformity all at the same time.
Another disadvantage of the prior art is that plating head or plating systems are bulky with large foot prints, which causes higher cost of ownership for users.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a novel method and apparatus for plating a metal film directly on a barrier layer without using a seed layer produced by a process other than plating.
It is a further object of the invention to provide a novel method and apparatus for plating a metal film over a thinner seed layer than employed in the prior art.
It is an additional object of the invention to provide a novel method and apparatus for plating a thin film with a more uniform thickness across a wafer.
It is a further object of the invention to provide a novel method and apparatus for plating a conducting film with a more uniform electrical conductivity across a wafer.
It is a further object of the invention to provide a novel method and apparatus for plating a thin film with a more uniform film structure, grain size, texture and orientation.
It is a further object of the invention to provide a novel method and apparatus for plating a thin film with an improved gap filling capability across a wafer.
It is a further object of the invention to provide a novel method and apparatus for plating a metal film for interconnects in an integrated circuit IC chip.
It is a further object of the invention to provide a novel method and apparatus for plating a thin film, with the method and apparatus having independent plating current control and electrolyte flow pattern control.
It is a further object of the invention to provide a novel method and apparatus for plating a metal thin film for a damascene process.
It is a further object of the invention to provide a novel method and apparatus for plating a metal film with a low impurity level.
It is a further object of the invention to provide a novel method and apparatus for plating copper with a low stress and good adhesion.
It is a further object of the invention to provide a novel method and apparatus for plating a metal film with a low addled particle density.
It is a further object of the invention to provide a novel plating system with a small footprint.
It is a further object of the invention to provide a novel plating system with a low cost of ownership.
It is a further object of the invention to provide a novel plating system which plates a single wafer at a time.
It is a further object of the invention to provide a novel plating system with an in-situ film thickness uniformity monitor.
It is a further object of the invention to provide a novel plating system with a built-in cleaning system with wafer dry-in and dry-out.
It is a further object of the invention to provide a novel plating system with a high wafer throughput.
It is a further object of the invention to provide a novel plating system which can handle a wafer size beyond 300 mm.
It is a further object of the invention to provide a novel plating system with multiple plating baths and cleaning/drying chambers.
It is a further object of the invention to provide a novel plating system with a stacked plating chamber and cleaning/dry chamber structure.
It is a further object of the invention to provide a novel plating system with automation features of the Standard Mechanical Interface (SMIF), the Automated Guided Vehicle (AGV), and the SEMI Equipment (Communication Standard/Generic Equipment Machine (SECS/GEM).
It is a further object of the invention to provide a novel plating system meeting Semiconductor Equipment and Materials International (SEMI) and European safety specifications.
It is a further object of the invention to provide a novel plating system with high productivity having a large mean time between failures (MTBF), small scheduled d
ACM Research, Inc.
Leader W. T.
Morrison & Foerster / LLP
Valentine Donald R.
LandOfFree
Plating apparatus and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Plating apparatus and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Plating apparatus and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2846495