Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-03-01
2002-07-02
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06415417
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technique for optimizing a transistor in designing an integrated circuit.
To develop a high-performance, high-density integrated circuit, each individual library cell composing the integrated circuit should be optimized in terms of the performance and area thereof. In particular, the load capacitance, driving capability, and area of a transistor greatly affect the performance and area of the library cell so that a technique for optimizing the transistor has been increasing in importance.
As a conventional method for transistor optimization, there is one using a model wherein a transistor is modeled using a constant resistance and the diffusion capacitance and area thereof are proportional to the transistor size (“TILOS: A posynomial programming approach to transistor sizing” J. P. Fishburn et al, Proc. Int. Conf. on Computer-Aided Design, 1985, pp. 326-328). Another conventional method for transistor optimization uses a more precise nonlinear model of the operation of a transistor to achieve higher accuracy (“Aesop: A tool for automate transistor sizing” Proc. Design Automation Conf., 1985, pp.
114-120).
Problems to be Solved
In an actual layout process, a transistor of a size larger than the height of a placement region is divided into a plurality of transistors which are connected in parallel and placed so that they share a diffusion region. This is termed “transistor folding” and a division number is termed a folding number (the number of folded portions). The area and diffusion capacitance of a transistor is affected by the folding.
In the conventional methods for transistor optimization, however, only the size of a transistor is the target of optimization and no consideration has not been given to the folding. The folding number is determined, during layout design, based on the transistor size determined without consideration of performance.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method for transistor optimization whereby the size of a transistor is optimized together with the folding number thereof.
Specifically, the present invention provides a method of optimizing, in designing an integrated circuit, a transistor composing the integrated circuit, the method comprising the step of optimizing a size and a folding number of the transistor so long as a given design constraint is satisfied by using a folding model in which a plurality of folding numbers are assumed for one transistor size.
In accordance with the invention, the size of the transistor is optimized together with the folding number thereof by using a folding model in which a plurality of folding numbers are assumed for one transistor size so long as the given design constraint is satisfied. Consequently, there can be designed an integrated circuit which has been improved in terms of area and performance.
In the method of optimizing a transistor in accordance with the present invention, an upper limit value of an area of the transistor is preferably given as the design constraint and an optimum combination of the size and the folding number that minimizes a delay so long as the area does not exceed the upper limit value is preferably determined. Moreover, the folding numbers in the folding model in the method of optimizing a transistor in accordance with the present invention are preferably assumed based on a lower limit value of the transistor size and on a height of a placement region for the transistor.
The present invention also provides a method of optimizing, in designing an integrated circuit, transistors composing the integrated circuit, the method comprising: a first step of calculating a performance improvement factor for each of the transistors when at least one of a size and a folding number of the transistor is changed; and a second step of selecting a type of the transistor change based on the calculated performance improvement factor and effecting the selected transistor change, the first and second steps being repeatedly performed to determine the size and folding number of the transistor.
In the method of optimizing a transistor in accordance with the present invention, the second step preferably includes selecting, as the type of the transistor change, a target transistor of changing and at least one of the size and folding number of the target transistor of changing. Alternatively, the second step in the method of optimizing a transistor in accordance with the present invention preferably includes selecting a type of the transistor change that maximizes the performance improvement factor. Alternatively, the second step in the method of optimizing a transistor in accordance with the present invention preferably includes calculating, for one of the transistors, the performance improvement factor when the size of the transistor is changed slightly for the same folding number and the performance improvement factor when the folding number is changed.
The present invention also provides a method of optimizing, in designing an integrated circuit, transistors composing the integrated circuit, the method comprising the steps of: obtaining a correlation curve between a delay and an area for each of a plurality of folding numbers of one of the transistors; obtaining a single postulated correlation curve for optimization based on the plurality of correlation curves obtained and on a common tangent to the individual correlation curves; and optimizing the size and folding number of the transistor in accordance with the correlation curve for optimization.
The present invention also provides a method for layout design of an integrated circuit, the method comprising the steps of: determining an optimum size of each of transistors together with an optimum folding number of the transistor based on a net list representing the integrated circuit and by using, as indices, performance of the integrated circuit and an area of the integrated circuit; and placing the transistor by using the size and folding number determined and generating a layout of the integrated circuit.
REFERENCES:
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patent: 5737236 (1998-04-01), Maziasz et al.
patent: 5995734 (1999-11-01), Saika
patent: 6163877 (2000-12-01), Gupta
patent: 5-326705 (1993-12-01), None
patent: 7-307448 (1995-11-01), None
Gupta et al. (“Optimal 2-D cell layout with integrated transistor folding”, 1998 IEEE/ACM International Conference on Computer-Aided Design, Nov. 8, 1998, pp. 128-135).*
Kim et al., (“An Efficient Transistor Folding Algorithm for Row-based Cmos Layout Design”, Proceedings of the 34th Design Automation Conference, Jun. 9, 1997, pp. 456-459).*
Gupta et al. (“XPRESS: a cell layout generator with integrated transistor folding”, Proceedings of European Design and Test Conference, Mar. 11, 1996, pp. 393-400).*
Her et al. (“Cell area minimization by transistor folding”, Proceedings of Design Automation Conference, Sep. 20, 1993, pp. 172-177).*
Hsich et al. (“LiB: a CMOS cell compiler”, IEEE Transactons on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, No. 8, Aug. 1991, pp. 994-1005).*
Li et al. (“Pull up transistor folding”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, No. 5, May 1990, pp. 512-521).*
Lursinsap et al. (“A technique for pull-up transistor folding”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, No. 8, Aug. 1988, pp. 887-896).*
van Genneken et al. (“Doubly folded transistor matrix layout”, IEEE International Conference on Computer-Aided Design, Nov. 7, 1988, pp. 134-137).*
“TILOS: A Posynomial Programming Approach to Transistor Sizing”, J.P. Fishburn et al., Proc. Int. Conf. on Computer-Aided Design, pp. 326-328, Jan. 1985.
“AESOP: A Tool for Automated Transistor Sizing”, K.S. Hedlund, Proc. Design Automation Conf., pp. 114-120, Jan. 1987.
U.S. patent application Ser. No. 09/034,382, Tanaka et al. filed Mar. 4, 1998.
Fukui Masahiro
Tanaka Masakazu
Kik Phallaka
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Smith Matthew
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