Out of order associative queue in two clock domains

Details Out of order associative queue in two clock domains Out of order associative queue in two clock domains

2000-09-20

2002-09-10

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S117000, C710S039000, C710S052000

Reexamination Certificate

active

06449701

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the field of memory controllers and, more particularly, to queues in memory controllers.
2. Description of the Related Art
Generally, memory controllers are used to interface various devices with a memory. Typically, the devices initiate transactions to read or write the memory on a bus, and the memory controller receives the transactions from the bus and performs the appropriate read or write operations to the memory.
In the past, buses have typically required that data for various transactions be returned in the same order that the corresponding addresses were presented on the bus. Accordingly, queues of transactions in memory controllers were typically first-in, first-out (FIFO) buffers. However, more recently, buses have become tagged, out of order buses in which data may be returned for transactions in any order as compared to the order that the corresponding addresses were presented. A tag, or transaction identifier, is presented on the bus concurrent with each address, and the tag is also presented when the data is transferred. Thus, the address and data portions of each transaction may be linked via the tag. Accordingly, improvements in memory queue design are needed to take advantage of the out of order nature of the buses.
Additionally, as synchronous dynamic random access memory (SDRAM) has become more popular, an additional difficulty has been faced by memory controller designs. The clock for the SDRAM memory may generally be of a different frequency than the bus clock, and may not be phase aligned to the bus clock. Thus, the memory controller may bridge two different clock domains: the bus clock domain and the memory clock domain. A memory controller with improved memory queue design which also handles the transitions between clock domains is therefore needed.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a memory controller as described herein. The memory controller may include a request queue for receiving transaction information (e.g. the address of the transaction) and a channel control circuit which controls a memory bus. A control circuit for the request queue may issue addresses from the request queue to the channel control circuit out of order, and thus the memory operations may be completed out of order. In one embodiment, the request queue shifts entries corresponding to transactions younger than a completing transaction to delete the completing transaction's information from the request queue. However, a data buffer for storing the data corresponding to transactions may not be shifted. Each queue entry in the request queue may store a data buffer pointer indicative of the data buffer entry assigned to the corresponding transaction. The data buffer pointer remains constant throughout the life of the transaction in the memory controller, and may be used to communicate between the channel control circuit, the request queue, and the control circuit.
In one implementation, the request queue may implement associative comparisons of information in each queue entry. For example, the transaction ID on the data bus may be associatively compared to transaction IDs in the entry to detect the data phases of transactions, which may be out of order with the corresponding address phases. Also, the data buffer pointers may be associatively compared to the data buffer pointer returned by the channel control circuit for communication regarding a particular transaction.
In one embodiment, the request queue and control circuit may be in the bus clock domain, while the channel control circuit may be in the memory clock domain. Thus, the interface between the channel control circuit and the request queue and control circuit may include acknowledgement of communications from the other clock domain to handle to the clock domain crossings.
Broadly speaking, a memory controller is contemplated. The memory controller may include a queue, a channel control circuit, and a control circuit. The queue is coupled to receive at least addresses of transactions from a bus, and the queue has a plurality of queue entries. Each of the plurality of queue entries is configured to store an address of a transaction and a pointer to a data buffer entry corresponding to the transaction. Coupled to the queue, the channel control circuit is configured to interface to a memory. Coupled to the queue and to the channel control circuit, the control circuit is configured to issue a first address of a first transaction and a first pointer to the data buffer entry corresponding to the first transaction. The channel control circuit is configured to acknowledge the first address by returning the first pointer to the queue.
Additionally, a method is contemplated. At least addresses of transactions are received from a bus into a queue having a plurality of queue entries. Each of the plurality of queue entries is configured to store an address of a transaction and a pointer to a data buffer entry corresponding to the transaction. A first address of a first transaction and a first pointer to a data buffer entry corresponding to the first address are issued to a channel control circuit. The first pointer is returned from the channel control circuit to acknowledge the issuing of the first address.


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patent: 6101568 (2000-08-01), Richardson
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Halfhill, “SiByte Reveals 64-bit Core for NPUs,” Microprocessor Report, Jun. 2000, pp. 45-48.

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