Method for nondestructively reading memory cells of an MRAM...

Details Method for nondestructively reading memory cells of an MRAM... Method for nondestructively reading memory cells of an MRAM...

2001-07-25

2002-05-14

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S173000, C365S171000, C365S210130

Reexamination Certificate

active

06388917

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
A memory cell of an MRAM (Magneto-Resistive Random Access Memory) is shown diagrammatically in FIG.
8
. In such a memory cell, the information to be stored is stored by the nature of the orientation of the magnetic moments in adjacent magnetized layers ML
1
and ML
2
, which are separated from one another by a very thin nonmagnetic intermediate layer TL, which is nonconductive. This is because the size of the electrical resistance across the memory cell depends on the parallel or antiparallel orientation of the magnetic moments in the magnetized layers ML
1
and ML
2
, that is to say the polarization thereof. In the case of the parallel orientation of the magnetic moments in the two layers ML
1
and ML
2
, the resistance of the memory cell is generally lower than in the case of their antiparallel orientation. This effect is also referred to as TMR effect (TMR=“tunneling magnetoresistive”) or as MTJ effect (MTJ=“magnetic tunnel junction”).
As a result, the memory content of the memory cell can be read out by detecting the resistance of the memory cell, the resistance being different for a “1” or “0”. Parallel magnetization of the two layers ML
1
and ML
2
may be assigned to a digital zero, for example, in which case the antiparallel magnetization of these layers corresponds to a digital one.
The change in resistance between the parallel and the antiparallel orientation of the magnetic moments in the magnetized layers ML
1
and ML
2
is physically based on the interaction of the electron spins of the conduction electrons in the thin nonmagnetic intermediate layer TL with the magnetic moments in the magnetized layers ML
1
and ML
2
of the memory cell. In this case, “thin” is intended to express the fact that the conduction electrons can cross the intermediate layer TL without spin scattering processes.
Preferably, the magnetization of one of the two magnetized layers ML
1
and ML
2
is coupled to an antiferromagnetic support or covering layer, as a result of which the magnetization in this magnetized layer remains essentially fixed, while the magnetic moment of the other magnetized layer can be freely oriented even in the case of small magnetic fields, as are generated for instance by a current in a word line WL and a bit line BL above and below the magnetized layer.
In a memory cell array, programming currents I
WL
and I
BL
flowing through the word line WL and through the bit line BL, respectively, are chosen such that a magnetic field strong enough for programming prevails only in the cell in which the word line WL crosses the bit line BL, by virtue of the sum of the two currents I
WL
and I
BL
, while all of the other memory cells present on this word line WL or this bit line BL cannot be reprogrammed by the current flowing only through one of these two lines.
FIG. 8B
once again diagrammatically illustrates the resistance R
c
of the memory cell between a bit line BL and a word line WL. The resistance R
c
is larger for the antiparallel orientation of the magnetic moments in the layers ML
1
and ML
2
than for the parallel orientation of the magnetic moments, i.e. R
c
(“0”) <R
c
(“1”), if the above assumption for the assignment of a “
1
” or a “0” is taken as a basis.
In their simplest embodiment, MRAMs include interconnects—crossing one another in a matrix form—of the word lines WL and of the bit lines BL, via which the memory cells are addressed. An upper interconnect, for example the bit line BL (cf. FIG.
8
A), is in this case connected to the upper magnetized layer ML
1
, e.g. a ferromagnetic layer, while the lower interconnect, which forms the word line WL, bears against the lower magnetized layer ML
2
, which may likewise be a ferromagnetic layer. If a voltage is applied to the memory cell via the two interconnects for the word line WL and the bit line BL, then a tunneling current flows through the thin nonmagnetic intermediate layer TL. This thin nonmagnetic intermediate layer then forms the resistance R
c
(See
FIG. 8B
) which, depending on the parallel or the antiparallel orientation of the magnetic moments, that is to say the parallel or the antiparallel polarization of the upper and lower ferromagnetic layers, given a suitable voltage across the memory cell, assumes the magnitude R
c
(“0”)<R
c
(“1”) or R
c
(“1”)=R
c
(“0”)+&Dgr;R
c
.
FIG. 9
shows a memory cell array in which memory cells are configured like a matrix at crossover points between word lines WL and bit lines BL.
The cell content is indicated diagrammatically here depending on the antiparallel or parallel polarization as a “1” or a “0” for two memory cells.
In a memory cell array as shown diagrammatically in
FIG. 9
, not only does a current flow via the memory cell at the crossover point between a selected word line WL and a selected bit line BL, but undesirable shunt currents also occur at further memory cells which are respectively connected to the selected word line WL and the selected bit line BL. These undesirable shunt currents interfere to a considerable extent with the read current which flows through the selected memory cell.
Therefore, efforts have already been made to use suitable circuitry of the memory cell array to largely separate such undesirable shunt currents from the read current, so that only the read current through the selected memory cell or the read voltage across the memory cell is available for detection. In this case, however, because of the parasitic currents flowing through the other memory cells, the resistance of the memory cells must be chosen to be high, in particular in the Mohm range, in order to be able to construct sufficiently large memory cell arrays.
Another way of avoiding the undesirable shunt currents is to augment the inherently simply constructed MTJ memory cell (cf.
FIG. 10
a
) with a diode D (cf.
FIG. 10
b
) or with a switching transistor T (cf.
FIG. 10
c
) (R. Scheuerlain et al., “A 10 ns Read and Write Time Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET-Switch in each Cell”, ISSCC February. 2000 p. 128/R.c. Sousa et al., “Vertical Integration of a spin dependent tunnel junction with an amorphous Si diode”, appl. Phys. Letter Vol. 74, No. 25, pp. 3893 to 3895).
The advantage of such augmentation by a diode or a switching transistor is that, in the memory cell array, given suitable circuitry, a read current only flows through the memory cell that is respectively read, since all of the remaining memory cells are inhibited. The resistance of the memory cell can then be chosen to be lower in contrast to a pure MTJ cell in accordance with
FIG. 10
a,
as a result of which the read current becomes relatively large and the read-out can take place rapidly in the ns range. Such additional circuitry with a diode or a transistor has the disadvantage, however, that it causes considerable additional technological and areal outlay.
In the current state of the art, it is a common feature of all memory cell types that it is very difficult to detect or evaluate a read signal as “0” or “1” since the tunneling resistance formed by the layer sequence of the layers ML
1
, TL and ML
2
generally fluctuates, not only over a wafer but even in many cases between adjacent memory cells, to a much greater extent, i.e. up to 40%, than the difference in the resistance &Dgr;R
c
between a “1” state and a “0” state, which is just 15%, for example. In other words, these conditions make it considerably more difficult or even impossible to reliably detect the content of a memory cell.
In other memory types that differ from MRAMs, a “1” or a “0” is detected from a current or a voltage read signal by comparing the read signal with either a reference current or a reference voltage, which should have a value midway between the read current or the read voltage for a “1” and the read current or the read voltage for a “0” in order to achieve the best signal-to-noise ratio in each case for both digital values. The reference current or the reference voltage can be generated by means o

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